Application Synthesis for MPSoCs Implementation Using Multiobjective Optimization

Silva, Marcus Vinícius; Nedjah, Nadia; Mourelle, Luiza Macedo

doi:10.1007/978-3-642-02478-8_92

Cited by 2 publications

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“…Note that, GA portion of this execution model is different from the previously proposed techniques (Ascia et al 2004;Zhou et al 2006;da Silva et al 2009). However, it still shows the affects of separating processor selection from mapping.…”

Section: Resultsmentioning

confidence: 93%

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Heterogeneous network-on-chip design through evolutionary computing

Öztürk

Demirbas

2010

International Journal of Electronics

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This article explores the use of biologically inspired evolutionary computational techniques for designing and optimising heterogeneous network-on-chip (NoC) architectures, where the nodes of the NoC-based chip multiprocessor exhibit different properties such as performance, energy, temperature, area and communication bandwidth. Focusing primarily on array-dominated applications and heterogeneous execution environments, the proposed approach tries to optimise the distribution of the nodes for a given NoC area under the constraints present in the environment. This article is the first one, to our knowledge, that explores the possibility of employing evolutionary computational techniques for optimally placing the heterogeneous nodes in an NoC. We also compare our approach with an optimal integer linear programming (ILP) approach using a commercial ILP tool. The results collected so far are very encouraging and indicate that the proposed approach generates close results to the ILP-based approach with minimal execution latencies. © 2010 Taylor & Francis

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Section: Resultsmentioning

confidence: 93%

“…In the next set of experiments, we include an additional execution model to reflect the behaviour of the studies (Ascia et al 2004;Zhou et al 2006;da Silva et al 2009) described in Section 2. Recall that, these studies try to map IPs or processors onto the NoC using a GA-based framework with different objectives.…”

Section: Resultsmentioning

confidence: 99%

Heterogeneous network-on-chip design through evolutionary computing

Öztürk

Demirbas

2010

International Journal of Electronics

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Optimal IP Assignment for Efficient NoC-based System Implementation using NSGA-II and MicroGA

Silva

Nedjah²,

Mourelle³

2009

International Journal of Computational Intelligence Systems

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Network-on-chip (NoC) are considered the next generation of communication infrastructure, which will be omnipresent in most of industry, office and personal electronic systems. In platform-based methodology, an application is implemented by a set of collaborating intellectual properties (IPs) blocks. In this paper, we use two multi-objective evolutionary algorithms to address the problem of selecting the most adequate set of IPs (from an available library) that best implements the application. The IP selection optimization is driven by the minimization of hardware area, total execution time and power consumption.

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Application Synthesis for MPSoCs Implementation Using Multiobjective Optimization

Cited by 2 publications

References 1 publication

Heterogeneous network-on-chip design through evolutionary computing

Heterogeneous network-on-chip design through evolutionary computing

Optimal IP Assignment for Efficient NoC-based System Implementation using NSGA-II and MicroGA

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