Application-specific instruction generation for configurable processor architectures

Cong, Jason; Fan, Yiping; Han, Guoling; Zhang, Zhiru

doi:10.1145/968280.968307

Cited by 193 publications

(164 citation statements)

References 19 publications

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“…Then the code of each kernel will be converted to a directed acyclic graph (DAG) representation. This work can be easily done with the SUIF compiler [14] focuses on reusability of each CI [8], whereas the other focuses on performance gain of a single CI [7]. There is no guarantee that one methodology can beat the other one.…”

Section: Previous Workmentioning

confidence: 99%

See 1 more Smart Citation

Fast Generation of Multiple Custom Instructions under Area Constraints

Wu¹,

Lee²,

Ahn³

et al. 2011

JSTS:Journal of Semiconductor Technology and Science

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Abstract-Extensible processors provide an efficient mechanism to boost the performance of the whole system without losing much flexibility. However, due to the intense demand of low cost and power consumption, customizing an embedded system has been more difficult than ever. In this paper, we present a framework for custom instruction generation considering both area constraints and resource sharing. We also present how we can speed up the process through pruning and library-based design space exploration.

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Section: Previous Workmentioning

confidence: 99%

“…There have been many researches on automatic CI generation [5][6][7][8][9][10][11][12][13], and many different methodologies have been developed to solve partial problems. However, none of them studied generating CIs considering both area constraints and resource sharing.…”

Section: Introductionmentioning

confidence: 99%

Fast Generation of Multiple Custom Instructions under Area Constraints

Wu¹,

Lee²,

Ahn³

et al. 2011

JSTS:Journal of Semiconductor Technology and Science

View full text Add to dashboard Cite

show abstract

“…As this method dose not consider the situation of overlapping subgraphs, it loses more opportunities for speedup. Work by Cong [6] attacked the same problem by using a binate covering formulation and the overlapping subgraphs are allowed. But the risks of mapping confusion for accelerator are increased during the code generation phase.…”

Section: Introductionmentioning

confidence: 99%

An Efficient Method for Custom Instruction Mapping Under the Safety Assurance of Code Generation

Luo¹,

Yuchun²,

Wu³

2014

Proceedings of the 3rd International Conference on Computer Science and Service System

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Abstract-In the work flow of embedded systems, processor design is the critical technology to directly affect the performance of whole system. In this process, instruction mapping is responsible for identifying the portions of target application program which match with custom instruction (CI) and implementing code generation for extension processor. However, traditional instruction mapping approaches would not consider the problem of mapping safety so that the mapping result is not reliable. In addition, as target applications get more complex, the drawback of large time cost makes embedded system less efficient. In this paper, we build safety check to ensure that the matched subgraphs can really be executed by hardware accelerator. And we propose an efficient matching method according the logic information of application program to reduce matching time and search space. For overlapping matched subgraphs, we also build up Maximal Weight Independent Set-based model to obtain better speedup of extension processor and the experiment results show the superiority of our method.

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“…Trimaran. In [1] [2] [3] [4], various identification algorithms are used to rapidly indentify a set of CI candidates from DFG (Data Flow Graph). Generation stage mainly selects lesser subgraphs from candidates as final CIs.…”

Section: Introductionmentioning

confidence: 99%

An Effective Strategy of Area Reduction for Custom Instruction Based on Basic Cell

Liu¹,

Ma²,

Wu³

2014

Proceedings of the 3rd International Conference on Computer Science and Service System

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Abstract-Area reduction is very important for CI (Custom Instruction) on reconfigurable processor. However, for FPGA (Field Programmable Gate Array) structure, resource sharing method is inefficient for area reduction of data-path. In the paper, we propose an effective strategy of area reduction for custom instruction. Firstly, we partitioned data-path of the final CI to lots of BCs (Basic Cells). Then we checked all the validity of BCs to make sure that each BC can be realized using single logic element of FPGA, and selected the unique BC set to overlap original data-paths. Finally, on the basis of BC partitioning, we adopt an approach of Merging CIs to reduce area cost of data-path, which is different from traditional method of resource sharing. Experiment results show that basic cell can really represent FPGA architecture, compared to a method of efficient resource sharing, the approach of merging CIs based on BC can lead to more than 11% average reduction of area.

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Application-specific instruction generation for configurable processor architectures

Cited by 193 publications

References 19 publications

Fast Generation of Multiple Custom Instructions under Area Constraints

Fast Generation of Multiple Custom Instructions under Area Constraints

An Efficient Method for Custom Instruction Mapping Under the Safety Assurance of Code Generation

An Effective Strategy of Area Reduction for Custom Instruction Based on Basic Cell

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