Application Space Exploration of a Heterogeneous Run-Time Configurable Digital Signal Processor

Rossi, Davide; Mucci, Claudio; Campi, Fabio; Spolzino, S.; Vanzolini, Luca; Sahlbach, Henning; Whitty, Sean; Ernst, Rolf; Putzke-Röming, Wolfram; Guerrieri, R.

doi:10.1109/tvlsi.2012.2185963

Cited by 14 publications

(3 citation statements)

References 28 publications

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“…Hence SoCs provide the best system flexibility, combining software-and hardware-programmability. In one pioneering work [26] the eFPGA is used for reconfigurable I/Os while in the systems proposed in [27] and [37] the eFPGA is adopted for custom peripherals and accelerators e.g. binarization and Ethernet MAC.…”

Section: System-on-chipsmentioning

confidence: 99%

A Fully Programmable eFPGA-Augmented SoC for Smart Power Applications

Renzini

Mucci

Rossi

et al. 2020

IEEE Trans. Circuits Syst. I

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This paper proposes a reconfigurable System-on-Chip (SoC) for smart power applications. The system is composed of an ultra-low-power microcontroller for standard software programmability, coupled to an embedded-FPGA (eFPGA) to perform control-driven applications and lightweight digital signal processing, at a lower power consumption and higher responsiveness than with processor-based execution. To the best of the authors' knowledge this is the first heterogeneous reconfigurable SoC targeting smart power applications. The SoC targets BCD technologies integrating Bipolar, CMOS and DMOS devices, typically featuring a small amount of metal layers when compared to traditional CMOS technologies. The added value of the proposed system is that the digital system is fully synthesizable, since the eFPGA is based on a soft-core approach. The paper presents the results of integrating an eFPGA with a computational capability of 1k equivalent gates in STMicroelectronics 90 nm BCD technology featuring five metal layers and high-k transistors. We benchmarked our architecture on a wide range of applications relevant to the smart power domain. eFPGA integration in SoCs introduces a 20-27% area overhead, but has a straightforward benefit in terms of energy consumption which proves reduced from about 10× to 800×. In terms of latency, the eFPGA implementation allows a gain from 8× to 145× comparing the pure cycles count.

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Section: System-on-chipsmentioning

confidence: 99%

A Fully Programmable eFPGA-Augmented SoC for Smart Power Applications

Renzini

Mucci

Rossi

et al. 2020

IEEE Trans. Circuits Syst. I

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“…Furthermore, multi-accelerators will inevitably induce extra communication congestion, thus reducing the overall throughput rate [11].…”

Section: Introductionmentioning

confidence: 99%

Design and Application Space Exploration of a Domain-Specific Accelerator System

Feng

Wang

et al. 2018

Electronics

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Domain-specific accelerators are a reaction adapting to device scaling and the dark silicon era. This paper describes a radar signal processing oriented configurable accelerator and the application space exploration of the system. The system is built around accelerator engines and general-purpose processors (GPPs) that make it suitable for intensive computing kernel acceleration and complex control tasks. It is geared toward high-performance radar digital signal processing; we characterize the applications and find that each of them contains a series of serializable kernels. Taking advantage of this discovery, we design an algorithm pool that shares the same computation resource and memory resource, and each algorithm is size reconfigurable. On the other hand, shared on-chip addressable scratchpad memory eliminates unnecessary explicit data copy between accelerators. Performance of the system is evaluated from measurements performed both on an FPGA SoC test chip and on a prototype chip fabricated by CMOS 40 nm technology. The experimental results show that for different algorithms, the proposed system achieves 1.9× to 10.1× performance gain compared with a state-of-the-art TI DSP chip. In order to characterize the application of the system, a complex real-life task is adopted, and the results show that it can obtain high throughput and desirable precision.

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“…Numerous efficient implementations of video codec standards on reconfigurable architectures have been achieved (e.g. extreme processing platform (XPP) [20, 21], multimedia oriented reconfigurable architecture (MORA) [22] and reconfigurable multi‐media system (REMUS) [23–25]). However, reconfigurable implementations of an HEVC in‐loop filter do not appear in the available literature.…”

Section: Introductionmentioning

confidence: 99%