370278-6648/08/$25.00 © 2008 IEEE I NEXPENSIVE MICROPROCESSOR-BASED EQUIPMENT, ranging from economy-model personal computers to microcontrollers for appliances and automobiles, is prone to computational errors because it does not have the error-correcting hardware resources of more costly top-ofthe-line equipment. This low-cost equipment is subject to bit errors from inevitable disturbances such as electrical surges, transient voltages, and cosmic rays.Such bit errors can be surprisingly frequent. According to field studies, a single 16-Mb dynamic random-access memory (DRAM) may have an error rate of 52,000 FITs (1 FIT = 1 failure in 10 9 hours), corresponding to a failure rate of about one per week. This would be an unacceptable failure rate when safety is at stake, as in automotive, avionics, and industrial microcontrollers.Fortunately, there is a strategy to circumvent such errors: use software to detect errors and when they occur, recompute the data. This is a far less costly way to avoid failures than providing error correction in the form of redundant circuitry. It substitutes time redundancy (on the order of two) for hardware redundancy.This article presents a new error detection scheme for implementing that strategy: the PSW-NOP method. Figure 1 illustrates the principle. Briefly, the method examines the processor status word (PSW) bit pattern to see if it remains unchanged during execution of a code. Under normal circumstances, the PSW should not change; a change indicates that an operational or microprocessor fault has occurred. In this scheme, several no-operation (NOP) instructions, preceded and followed by PSW instructions, are executed. The PSWs before and after execution are stored in a stack, then popped and compared in order to check the similarity of the corresponding flag bits of both PSWs. Execution of the NOP codes should not alter the PSW flag bit patterns; hence, the before and after flags should be similar unless an electrical transient-a fault-has corrupted them.