Application-oriented wear-leveling optimization of 3D TSV-integrated storage class memory-based solid state drives

Nakanishi, Masaru; Adachi, Yutaka; Matsui, Chihiro; Sugiyama, Yusuke; Takeuchi, Ken

doi:10.23919/icep.2018.8374663

Cited by 3 publications

(2 citation statements)

References 11 publications

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“…Three-dimensional integrated circuits (3D-IC) have received significant attention because they have the potential to improve IC performances beyond those offered by the scaling of transistors [1]. 3D-ICs consist of several vertically stacked chips, electrically connected by through-Si vias (TSVs) and metal microbumps; they have been developed for several applications, such as memory storage and processors [2]- [5]. RF applications, which consist of mixed-signal ICs, are a class of applications that benefit greatly from 3D integration [6]- [8].…”

Section: Introductionmentioning

confidence: 99%

Investigation of TSV Liner Interface With Multiwell Structured TSV to Suppress Noise Propagation in Mixed-Signal 3D-IC

Kino

Fukusima

Tanaka

2019

IEEE J. Electron Devices Soc.

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Mixed-signal 3D-ICs have a stacked structure of digital and analog circuit chips. In this study, the effect of noise propagation from a digital circuit on an analog circuit was evaluated using an actual mixed-signal 3D-IC. The noise propagation via through-silicon vias (TSVs) was measured, with a ring-oscillator as a noise source. For a comprehensive investigation, TSV-liner interface states were evaluated along the depth direction using unique multiwell-structured TSVs and a charge-pumping method. It was considered that the interface traps and nonconformal thickness of the TSV liner increased the noise propagation among stacked chips.INDEX TERMS 3D IC, through-silicon vias, charge pumping method, interface trap.

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Section: Introductionmentioning

confidence: 99%

Investigation of TSV Liner Interface With Multiwell Structured TSV to Suppress Noise Propagation in Mixed-Signal 3D-IC

Kino

Fukusima

Tanaka

2019

IEEE J. Electron Devices Soc.

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“…Figure 1 shows a comparison among 3D integration methods. The 3D stacking processes are generally divided into two categories: chip-to-chip (C2C) 7,12,16) and wafer-towafer (W2W). [17][18][19][20] The C2C process is based on one-by-one known good dies (KGD) pick-and-place.…”

Section: Introductionmentioning

confidence: 99%

Multichip thinning technology with temporary bonding for multichip-to-wafer 3D integration

Lee

Liang

Miwa

et al. 2019

Jpn. J. Appl. Phys.

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Thinning defects such as chipping and cracking caused by multichip lapping and chemical mechanical polishing processes were evaluated for through-silicon via formation based on via-last/backside via technologies. Two types of temporary adhesives with different Young's moduli were used in this multichip-to-wafer (MC2W) approach for comparison. Impact of the temporary bonding conditions and temporary adhesive properties on the multichip thinning failure was discussed for achieving high-yield MC2W 3D integration. When a temporary adhesive with a low Young's modulus is employed, the space between adjacent chips and the chip sidewall covered with adhesive were found to be critical parameters to the multichip thinning without chipping and cracking.

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3D Dislocation Multi-stack Fan-out Package of Ultra-thin Dies for Heterogeneous Integration

Chen

Dai

2021

2021 22nd International Conference on Electronic Packaging Technology (ICEPT)

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Application-oriented wear-leveling optimization of 3D TSV-integrated storage class memory-based solid state drives

Cited by 3 publications

References 11 publications

Investigation of TSV Liner Interface With Multiwell Structured TSV to Suppress Noise Propagation in Mixed-Signal 3D-IC

Investigation of TSV Liner Interface With Multiwell Structured TSV to Suppress Noise Propagation in Mixed-Signal 3D-IC

Multichip thinning technology with temporary bonding for multichip-to-wafer 3D integration

3D Dislocation Multi-stack Fan-out Package of Ultra-thin Dies for Heterogeneous Integration

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