Application of principal component analysis based effective digital predistortion technique for low-cost FPGA implementation

Abstract

This article investigates the issue of low-cost digital predistortion (DPD) implementation in fixed-point field programmable gate array (FPGA) by considering the bitresolution along with lower number of coefficients. The impact of principle component analysis (PCA) on bit-resolution of DPD solution is proposed within the context of established DPD models. Unlike previously proposed PCA based solutions, it is established by simulation and measurement that the numerical stability problem associated with popular models such as memory polynomial (MP) can be alleviated when PCA is applied to the observation data matrix. It is reported with measurement results that PCA based model provides better linearization performance with the least memory size requirement and number of LUTs in 16-bit fixed-point FPGA operation than MP, orthogonal memory polynomial (OMP), and generalized memory polynomial (GMP) models. The performance of the proposed model, is evaluated in terms of normalized mean square error, adjacent channel error power ratio, matrix condition number, and dispersion coefficient for continuous Class-AB and ZX60-V631 power amplifiers using wide code-division multiple access signal (WCDMA) and long term evolution (LTE) signal with peak-to-average-power ratio (PAPR) around 9.895 and 11.92 dB, respectively. K E Y W O R D S behavioral modeling, digital predistortion (DPD), memory effect, memory polynomial (MP), order reduction, power amplifier (PA), principal component analysis (PCA) Int J RF Microw Comput Aided Eng. 2017;27:e21095.

2D curtailed harmonic memory polynomial for reduced complexity in concurrent dual‐band modelling and digital predistortion with the second band at harmonic frequency

“…The coefficients extracted while performing inverse modelling for different models in Section 4.2 at different fixed-point bitresolutions are used to generate predistorted signal for different models. Table 6 shows the DPD performances performed at different fixed-point bit (16,24, and 32) resolutions for both measurement set-ups. The 2D-HMP-PCA, and 2D-CHMP-PCA DPD have good performance at 16-bit resolution, however, the 2D-HMP-PCA model requires more number of coefficients than the 2D-CHMP-PCA model.…”

“…The FPGA's memory size required by a model depends on the size of observation (predistorter) matrix and bit-resolution of each sample [23,24]. Memory~size = Matrix size × Bit-sesolution (22) where matrix size = L × no .…”

“…For efficient low-bit implementation, a DPD model required to be numerically stable. In [24], PCA-based effective single-band DPD technique for low-bit FPGA implementation was proposed. In [25], the PCA technique was applied upon the 2D-HMP model to reduce the number of coefficients, size of observation (predistorter) matrix, condition number and dispersion coefficient.…”

Digital predistortion technique for low resource consumption using carrier aggregated 4G/5G signals

“…After extracting the coefficients, the inverse modelling performance is evaluated in terms of normalised mean square error (NMSE) and adjacent channel error power ratio (ACEPR). NMSE is mathematically defined as [27]…”

“…where e(n) = y meas (n) − y est (n) is the error between the measured baseband output signal y meas (n) and the estimated model output y est (n) for any sample n. ACEPR is mathematically defined as [27]…”