Application of on-chip MIM decoupling capacitor for 90nm SOI microprocessor

Roberts, D.; Johnstone, Walter; Sanchez, H.; Mandhana, O.P.; Spilo, D.; Hayden, J.D.; Travis, E.; Melnick, B. M.; Celik, M.; Min, B.; Edgerton, Jeremy R.; Raymond, M.; Luckowski, E.; Happ, C.; Martínez, Arturo; Wilson, B.; Leung, Pak Sing; Garnett, T.; Goedeke, D.; Remmel, T.; Ramakrishna, K.; White, Bruce

doi:10.1109/iedm.2005.1609269

Cited by 14 publications

(11 citation statements)

References 1 publication

Supporting

Mentioning

Contrasting

Order By: Relevance

“…This behavior occurs since the signal at the input of a distributed filter is degraded by the resistance and the input impedance of the filter , forming a voltage divider. To produce the duty cycle required for a specific DC voltage, consider the input impedance of the filter at DC (24) where , and are defined in (16), and is the DC component of the current load (6). The DC component of the signal at the input of the filter (including in Fig.…”

Section: ) Transfer Function Of a 3-d Filtermentioning

confidence: 99%

See 1 more Smart Citation

Linear and Switch-Mode Conversion in 3-D Circuits

Rosenfeld

Friedman

2011

IEEE Trans. VLSI Syst.

View full text Add to dashboard Cite

Abstract-A methodology for DC-DC conversion in three-dimensional (3-D) circuits is described in this paper. The proposed approach exploits both linear and switching buck converters with different conversion ranges, thereby increasing power efficiency. By replacing the traditional LC filter within a switching converter with a distributed filter, a significant increase in efficiency is demonstrated. Additionally, the physical structure of the filter simultaneously enables the distribution of high current to the load while filtering the switching signal at the input. Design guidelines and expressions are developed, achieving good agreement with simulations based on the MIT Lincoln Laboratories CMOS/SOI 180-nm 3-D technology. The proposed converter distributes 2.5 A maximum current, achieving conversion from 3.3 V to 2.5 V and 1 V with, respectively, 74% and 44% power efficiency.Index Terms-3-D integrated circuits, DC-DC buck converters, power efficiency.

show abstract

Section: ) Transfer Function Of a 3-d Filtermentioning

confidence: 99%

“…11) is (27) where is the rms voltage of the input signal, is the effective output resistance of the power MOSFETs and , and is the input impedance of the filter network at (24). The output power at the load of the filter is…”

Section: B Power Losses Of Switching Converter With Distributed Filtermentioning

confidence: 99%

Linear and Switch-Mode Conversion in 3-D Circuits

Rosenfeld

Friedman

2011

IEEE Trans. VLSI Syst.

View full text Add to dashboard Cite

show abstract

“…In [20], high performance ALD HfO2-Al2O3 laminate MIM capacitor is fabricated with high capacitance density of 12.8f F/μm 2 (for reference, at the 90nm node the capacitance density of CMOS capacitors can be estimated as εox/tox = 17.3f F/μm 2 , where εox is the dielectric constant and tox ≈ 20Å is the thickness of oxide). A successful implementation of large-area MIM capacitors (exceeding 250nF ) in the power grid of a 90nm SOI microprocessor, with up to 8f F/μm 2 capacitance density, is reported in [24]. A significant advantage of MIM decaps lies in their extremely low leakage: in [24], the leakage current for the 250nF MIM decaps is reported to be about 1.…”

Section: Introductionmentioning

confidence: 99%

“…A successful implementation of large-area MIM capacitors (exceeding 250nF ) in the power grid of a 90nm SOI microprocessor, with up to 8f F/μm 2 capacitance density, is reported in [24]. A significant advantage of MIM decaps lies in their extremely low leakage: in [24], the leakage current for the 250nF MIM decaps is reported to be about 1. Figure 2 shows an example with CMOS and MIM decaps in one tier of a 3D circuit.…”

Section: Introductionmentioning

confidence: 99%

Congestion-aware power grid optimization for 3D circuits using MIM and CMOS decoupling capacitors

Zhou

Sridharan

Sapatnekar

2009

2009 Asia and South Pacific Design Automation Conference

View full text Add to dashboard Cite

Abstract-In three-dimensional (3D) chips, the amount of supply current per package pin is significantly more than in two-dimensional (2D) designs. Therefore, the power supply noise problem, already a major issue in 2D, is even more severe in 3D. CMOS decoupling capacitors (decaps) have been used effectively for controlling power grid noise in the past, but with technology scaling, they have grown increasingly leaky. As an alternative, metal-insulator-metal (MIM) decaps, with high capacitance densities and low leakage current densities, have been proposed. In this paper, we explore the tradeoffs between using MIM decaps and traditional CMOS decaps, and propose a congestion-aware 3D power supply network optimization algorithm to optimize this tradeoff. The algorithm applies a sequence-of-linear-programs based method to find the optimum tradeoff between MIM and CMOS decaps. Experimental results show that power grid noise can be more effectively optimized after the introduction of MIM decaps, with lower leakage power and little increase in the routing congestion, as compared to a solution using CMOS decaps only.

show abstract

“…One of the novel features of our work is that it optimizes the power supply network using both conventional CMOS decaps and MIM decap technology, illustrated in Figure 1, which has high capacitance density and low leakage current density [6]- [8]. However, since MIM decaps are built between layers of metal interconnects, they present routing blockages to nets that attempt to cross them, and therein lies the tradeoff.…”

mentioning

confidence: 99%

Power Grid Optimization in 3D Circuits Using MIM and CMOS Decoupling Capacitors

Sapatnekar

Zhou

Sridharan

2011

IEEE Des. Test. Comput.

View full text Add to dashboard Cite

Abstract-In three-dimensional (3D) chips, the amount of supply current per package pin is significantly more than in twodimensional (2D) designs. Therefore, the power supply noise problem, already a major issue in 2D, is even more severe in 3D. CMOS decoupling capacitors (decaps) have been used effectively for controlling power grid noise in the past, but with technology scaling, they have grown increasingly leaky. As an alternative, metal-insulator-metal (MIM) decaps, with high capacitance densities and low leakage current densities, have been proposed. In this paper, we explore the tradeoffs between using MIM decaps and traditional CMOS decaps, and propose a congestion-aware 3D power supply network optimization algorithm to optimize this tradeoff. The algorithm applies a sequence-of-linear-programs based method to find the optimum tradeoff between MIM and CMOS decaps. Experimental results show that power grid noise can be more effectively optimized after the introduction of MIM decaps, with lower leakage power and little increase in the routing congestion, as compared to a solution using CMOS decaps only, and motivate the stronger need for these decaps in 3D technology, as compared to 2D designs.Index Terms-MIM decap, CMOS decap, Power grid, 3DI. INTRODUCTION Three dimensional (3D) circuit technologies, with multiple tiers of active devices stacked above each other, are a key approach to increased levels of integration and performance in the future. However, there are two significant limitations that 3D technologies must overcome before achieving their full potential, related to on-chip thermal issues and reliable power delivery. Both issues can be illustrated through a simple back-of-the-envelope calculation. A k-tier 3D chip that stacks k similar chips could use k times as much current as a single 2D chip of the same footprint. However, the packaging technology is not appreciably different: with a similar heat sink, the on-chip temperature on such a 3D chip can be up to k times higher than the 2D chip, and with a similar number of pins in the package, the current per pin is k times higher than the 2D case.The above analysis operates under very coarse assumptions (for example, a smart 3D designer may not stack k layers with identical power levels), and a more nuanced approach is necessary for a more accurate analysis -but the eventual conclusions that thermal and power delivery issues are important in 3D -are inescapable. While much research has been conducted on thermal management strategies such as thermal via insertion, and the spatial distribution of power sources, the power delivery problem has attracted limited attention to date.The power delivery problem can be summarized as follows. The parasitics in the power network, together with temporal variations in the current drawn by a circuit, result in a time-varying voltage drop/surge at nodes in the power grid. These variations can adversely impact the performance and the reliability of a circuit. Such shifts become more acute with technology scaling: on ...

show abstract

Application of on-chip MIM decoupling capacitor for 90nm SOI microprocessor

Cited by 14 publications

References 1 publication

Linear and Switch-Mode Conversion in 3-D Circuits

Linear and Switch-Mode Conversion in 3-D Circuits

Congestion-aware power grid optimization for 3D circuits using MIM and CMOS decoupling capacitors

Power Grid Optimization in 3D Circuits Using MIM and CMOS Decoupling Capacitors

Contact Info

Product

Resources

About