Application Example of a Novel Methodology to Generate IC Models for System ESD and Electrical Stress Simulation out of the Design Data

Ammer, Michael; Rupp, Andreas; Glaser, Ulrich; Cao, Yiqun; Sauter, Martin; Maurer, Linus

doi:10.23919/eos/esd.2019.8869981

Cited by 3 publications

(1 citation statement)

References 7 publications

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“…Previous researchers have conducted a large amount of research on the ESD effect of IC and accumulated a lot of ESD protection circuit design and simulation experience [ 8 , 9 ]. At present, the commonly used circuit modeling schemes are the black box model based on chip port signal and the SPICE model of devices [ 10 , 11 , 12 ].…”

Section: Introductionmentioning

confidence: 99%

Study on ESD Protection Circuit by TCAD Simulation and TLP Experiment

Chai

Liu

et al. 2023

Micromachines

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The anti-ESD characteristic of the electronic system is paid more and more attention. Moreover, the on-chip electrostatic discharge (ESD) is necessary for integrated circuits to prevent ESD failures. In this paper, the mixed TCAD model of the ESD protection circuit is built and simulated, and the negative transmission line pulse (TLP) injection damage experiment is carried out on the CD4069UBC chip. The circuit model consists of three-dimensional shallow trench isolation (STI) diode TCAD models and a three-dimensional multi-gate Complementary Metal-Oxide-Semiconductor (CMOS) inverter TCAD model. Moreover, the TCAD modeling is based on a 0.25 μm technology node. Through the transient simulation of the electrothermal coupling, the electrical signal of the input and output nodes of the circuit and the distribution of the electrothermal parameters in the device are obtained. Moreover, by analyzing the simulation results, the physical phenomena and the mechanisms of interference and damage mechanism during TLP injection are explained. The location and type of diode damage in the TLP injection simulation results of the circuit model are consistent with the TLP experiment damage results. The proposed ESD protection circuit model and analysis method are beneficial to ESD robustness prediction and ESD soft damage analysis of IC.

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