Application-driven synthesis of core-based systems

Kirovski,; Lee, Myeong Soo; Potkonjak,; Mangione-Smith,

doi:10.1109/iccad.1997.643382

Cited by 21 publications

(20 citation statements)

References 12 publications

(1 reference statement)

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“…The techniques proposed in [26], [30], and [40]- [42] are complementary to our approach since they can be applied as a preprocessing step. The techniques proposed in [26], [30], and [40] reduce the cache conflicts, while those proposed in [41] and [42] reduce the size of the cache or improve the performance of the cache, mainly by optimizing memory and cache data assignment. While the previous works concentrated on the memory and cache data assignment, our work considers other complementary issues such as processor selection, cache sizing, task scheduling, and voltage scheduling simultaneously.…”

Section: Paper Organizationmentioning

confidence: 99%

“…Panda et al [41] presented techniques to minimize data cache conflicts for direct-mapped caches by analyzing the array access patterns. Kirovski et al [26] developed techniques to minimize instruction/data cache conflicts for direct-mapped caches. The techniques proposed in [26], [30], and [40]- [42] are complementary to our approach since they can be applied as a preprocessing step.…”

Section: Paper Organizationmentioning

confidence: 99%

“…Kirovski et al [26] developed techniques to minimize instruction/data cache conflicts for direct-mapped caches. The techniques proposed in [26], [30], and [40]- [42] are complementary to our approach since they can be applied as a preprocessing step. The techniques proposed in [26], [30], and [40] reduce the cache conflicts, while those proposed in [41] and [42] reduce the size of the cache or improve the performance of the cache, mainly by optimizing memory and cache data assignment.…”

Section: Paper Organizationmentioning

confidence: 99%

See 2 more Smart Citations

Power optimization of variable voltage core-based systems

Hong¹,

Kirovski

et al. 1998

Proceedings of the 35th Annual Conference on Design Automation Conference - DAC '98

193

142

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Abstract-The growing class of portable systems, such as personal computing and communication devices, has resulted in a new set of system design requirements, mainly characterized by dominant importance of power minimization and design reuse. The energy efficiency of systems-on-a-chip (SOC) could be much improved if one were to vary the supply voltage dynamically at run time. We develop the design methodology for the lowpower core-based real-time SOC based on dynamically variable voltage hardware. The key challenge is to develop effective scheduling techniques that treat voltage as a variable to be determined, in addition to the conventional task scheduling and allocation. Our synthesis technique also addresses the selection of the processor core and the determination of the instruction and data cache size and configuration so as to fully exploit dynamically variable voltage hardware, which results in significantly lower power consumption for a set of target applications than existing techniques. The highlight of the proposed approach is the nonpreemptive scheduling heuristic, which results in solutions very close to optimal ones for many test cases. The effectiveness of the approach is demonstrated on a variety of modern industrialstrength multimedia and communication applications. Index Terms-High-level synthesis, scheduling, synthesis for low power, system-on-a-chip (SOC).

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Section: Paper Organizationmentioning

confidence: 99%

Section: Paper Organizationmentioning

confidence: 99%

Section: Paper Organizationmentioning

confidence: 99%

See 1 more Smart Citation

Power optimization of variable voltage core-based systems

Hong¹,

Kirovski

et al. 1998

Proceedings of the 35th Annual Conference on Design Automation Conference - DAC '98

193

142

View full text Add to dashboard Cite

show abstract

“…The architecture/compiler codesign of ASIPs is addressed in [7]. A method to search for a minimal-area processor core and cache, which satisfy the performance requirements of certain applications, is given in [8]. An ASIP design methodology for extending an existing processor instruction set architecture is described in [9].…”

Section: Introductionmentioning

confidence: 99%

A scalable application-specific processor synthesis methodology

Sun¹,

Ravi²,

Raghunathan³

et al. 2003

ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)

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Abstract-Custom processors based on application-specific or domain-specific instruction sets are gaining popularity, and are often used to implement critical architectural blocks in complex system-on-chips. While several advances have been made in custom processor architectures, tools, and design methodologies, designers are still required to manually perform some critical tasks, such as selection of the custom instructions best suited to the given application and design constraints.We present a scalable methodology for the synthesis of a custom processor from an embedded software program. A key feature of the proposed methodology is its scalability, which is achieved by exploiting the structured, hierarchical nature of large software programs. We motivate the need for such a methodology, and describe the algorithms used for the critical steps, including hardware resource budgeting, local optimizations, and global exploration. Our methodology utilizes the concept of "soft" instruction templates, which can be adapted by adding operations to them or deleting operations from them at any time during the design space exploration process, allowing for global design decisions to be interleaved with finegrained optimizations.We have integrated our methodology in an open source compiler, and verified it using a commercial extensible processor. Experiments with several benchmarks indicate that our methodology can effectively tackle large programs. It resulted in the synthesis of high-quality custom processors that demonstrated an average speedup of 2.61X and a maximum speedup of 6.32X. The CPU times required for custom processor synthesis were quite small, indicating that the proposed techniques can be applied to embedded software programs of significant complexity.

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“…We attack this problem by carefully scanning the design space using search algorithms with sharp bounds and by providing powerful algorithmic performance techniques. We use the system performance and simulation platform based on SHADE, DINEROIII and a custom analyzer [Kirovski et al 1997]. We conduct an exhaustive search for all the processor cores, I-cache (range from 512B to 32KB), D-cache (range from 4KB to 32KB) and cache line sizes (from 8B to 512B).…”

Section: Synthesis For Qos Guaranteed Soc Designmentioning

confidence: 99%

System synthesis of synchronous multimedia applications

Qu¹,

Mesarina²,

Potkonjak³

Proceedings 12th International Symposium on System Synthesis

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Modern system design is being increasingly driven by applications such as multimedia and wireless sensing and communications, which have intrinsic quality of service (QoS) requirements, such as throughput, error-rate, and resolution. One of the most crucial QoS guarantees that the system has to provide is the timing constraint among the interacting media (synchronization) and within each media (latency). We have developed the first framework for system design with timing QoS guarantees. In particular, we address how to design system-on-chip with minimum silicon area to meet both latency and synchronization constraints. The proposed design methodology consists of two phases: hardware configuration selection and on-chip memory/storage minimization. In the first phase, we use silicon area and system performance as criteria to identify all the competitive hardware configurations (i.e. Pareto points) that facilitate the needs of synchronous applications. In the second phase, we determine the minimum on-chip memory requirement to meet the timing constraints for each Pareto point. An overall system evaluation is conducted to select the best system configuration. We have developed optimal algorithms that schedule a-priori specified applications to meet their synchronization requirements with the minimum size of memory. We have also implemented on-line heuristics for real-time applications. The effectiveness of our algorithms have been demonstrated on a set of simulated MPEG streams from popular movies.

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Application-driven synthesis of core-based systems

Cited by 21 publications

References 12 publications

Power optimization of variable voltage core-based systems

Power optimization of variable voltage core-based systems

A scalable application-specific processor synthesis methodology

System synthesis of synchronous multimedia applications

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