Application-driven Cache-Aware Roofline Model

Marques, Diogo; Ilić, Aleksandar; Matveev, Zakhar A.; Sousa, Leonel

doi:10.1016/j.future.2020.01.044

Cited by 11 publications

(6 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Currently, we are collaborating with the developers of the Adaptive Cache Aware Roofline Method (adCARM) [44] to use hardware counters to support their method of tailoring rooflines to the specific application. This method provides the user with more realistic projections of potential performance, given the types of operations used by the kernel.…”

Section: Resultsmentioning

confidence: 99%

“…Two separate groups, Marques et al [44] and Cabezas and Püschel [45], extend the roofline to consider the instruction mixes of the application being studied. This allows the user to have more realistic expectations of the potential and a better understanding of which ceilings are limiting performance.…”

Section: Roofline Variationsmentioning

confidence: 99%

“…This metric is similar to Miss Rate but uses the LS Bytes as the denominator for all the levels of cache. In [44], the authors present a similar metric based on simulation data.…”

Section: Demonstration With Loop Blocking the Matrix Multiplication K...mentioning

confidence: 99%

See 2 more Smart Citations

Empirical Performance Analysis of HPC Applications with Portable Hardware Counter Metrics [Thesis]

Gravelle

2022

View full text Add to dashboard Cite

In this dissertation, we demonstrate that it is possible to develop methods of empirical hardware-counter-based performance analysis for scientific applications running on diverse CPUs. Although counters have been used in performance analysis for over 30 years, the methods remain limited to particular vendors or generations of CPUs. Our hypothesis is that counter-based measurements could be developed to provide consistent performance information on diverse CPUs. We prove the hypothesis correct by demonstrating one such set of metrics.We begin with an introduction and background discussing empirical performance analysis on CPUs. The background includes the Roofline Performance Model which is widely used to visualize the performance of scientific applications relative to the potential system performance. This model uses metrics that are portable to different CPU architectures, making it a useful starting point for efforts to develop portable hardware counter metrics. We contribute to existing roofline literature by presenting a method using counters to measure the required application data on two CPUs and by presenting benchmarks to produce the Roofline Model of the CPU. These contributions are complementary since the iv benchmarks can be used to validate the hardware counters used to measure the application data.We present a set of performance metrics derived from Hardware Performance Monitors that we have been able to replicate on CPUs from two vendors. We developed these metrics to focus on information that can inform developers about the performance of algorithms and data structures in applications. This method contrasts with other methods which are aimed at microarchitectural features and allows users to understand application performance from the same perspective on multiple CPUs.We use a series of case studies to explore the usefulness of our metrics and to validate that the measured values provide the expected information. The first set of studies examines benchmarks and mini-applications with a variety of performance. Finally, we study the performance of several versions of a scientific application using the Roofline Model and the new metrics. These case studies show that our performance metrics can provide performance information on two CPUs, proving our hypothesis by example.

show abstract

Section: Resultsmentioning

confidence: 99%

Section: Roofline Variationsmentioning

confidence: 99%

See 1 more Smart Citation

Empirical Performance Analysis of HPC Applications with Portable Hardware Counter Metrics [Thesis]

Gravelle

2022

View full text Add to dashboard Cite

show abstract

“…However, the arithmetic intensity used in the Original Roofline Model (ORM) is computed only from off-chip memory transfers between the Last Level Cache (LLC) and the DRAM, which is not sufficient to fully describe the performance of applications on modern hardware architectures. A more precise roofline model, referred to as Cache-Aware Roofline Model (CARM) (MARQUES et al, 2020;ILIC et al, 2013), also accounts for the on-chip memory traffic with data transfers between all cache levels, providing a more accurate behavior of the applications on computer systems designed with current hardware technology.…”

Section: Roofline Modelmentioning

confidence: 99%

Performance optimization of the MGB hydrological model for multi-core and GPU architectures

Freitas

Mendes

Ilić

2022

Environmental Modelling & Software

Self Cite

View full text Add to dashboard Cite

“…Ilic and Denoyelle have developed a toolset to create Cache-aware Roofline Models (CARMs) [8], [10], however, this toolset is based on microbenchmarks that use hardware specific details and are therefore not portable between different architectures. Recent works by Marques et al [11] still rely heavily on hand-coded microbenchmarks that target a specific architecture to extract the maximum performance from the machine. This has the significant limitation of restricting portability between systems.…”

Section: Roofline Model and Related Workmentioning

confidence: 99%

Autotuning Benchmarking Techniques: A Roofline Model Case Study

Torring¹,

Meyer²,

Elster³

2021

Preprint

View full text Add to dashboard Cite

Peak performance metrics published by vendors often do not correspond to what can be achieved in practice. It is therefore of great interest to do extensive benchmarking on core applications and library routines. Since DGEMM is one of the most used in compute-intensive numerical codes, it is typically highly vendor optimized and of great interest for empirical benchmarks.In this paper we show how to build a novel tool that autotunes the benchmarking process for the Roofline model. Our novel approach can efficiently and reliably find optimal configurations for any target hardware. Results of our tool on a range of hardware architectures and comparisons to theoretical peak performance are included.Our tool autotunes the benchmarks for the target architecture by deciding the optimal parameters through state space reductions and exhaustive search. Our core idea includes calculating the confidence interval using the variance and mean and comparing it against the current optimum solution. We can then terminate the evaluation process early if the confidence interval's maximum is lower than the current optimum solution. This dynamic approach yields a search time improvement of up to 116.33x for the DGEMM benchmarking process compared to a traditional fixed samplesize methodology. Our tool produces the same benchmarking result with an error of less than 2% for each of the optimization techniques we apply, while providing a great reduction in search time. We compare these results against hand-tuned benchmarking parameters. Results from the memory-intensive TRIAD benchmark, and some ideas for future directions are also included.

show abstract

Application-driven Cache-Aware Roofline Model

Cited by 11 publications

References 11 publications

Empirical Performance Analysis of HPC Applications with Portable Hardware Counter Metrics [Thesis]

Empirical Performance Analysis of HPC Applications with Portable Hardware Counter Metrics [Thesis]

Performance optimization of the MGB hydrological model for multi-core and GPU architectures

Autotuning Benchmarking Techniques: A Roofline Model Case Study

Contact Info

Product

Resources

About