Application-Based Metrics for Strategic Placement of Detectors

Pattabiraman, Karthik; Kalbarczyk, Zbigniew; Iyer, Ravishankar K.

doi:10.1109/prdc.2005.19

Cited by 48 publications

(46 citation statements)

References 13 publications

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“…Phase 2: Evaluating the accuracy of the DDG model We injected the faults considered by the DDG into a modified SimpleScalar simulator [13]. We modified sim-safe from SimpleScalar to mimic the behavior of the operating system when an application crashes [16]. As before, the fault length ranged from 2 to 10 nodes.…”

Section: Methodsmentioning

confidence: 99%

“…The dependencies are represented as edges in the graph, and are annotated based on the type of dependency (address/regular). DDGs have been used in prior work for understanding and analyzing program behavior [11], [12], [16]. To the best of our knowledge, we are the first to use DDGs in modeling the propagation of intermittent errors.…”

Section: Terms and Definitionsmentioning

confidence: 99%

“…The construction of the DDG uses established techniques [11], [16] and hence will not be elaborated here. Because we use T P S(i) in computing IP S(i s , i e ), we first explain how to compute T P S(i) below.…”

Section: Computing the Intermittent Fault Propagation Setmentioning

confidence: 99%

“…The DDG model: The DDG model has been used to derive information about programs in prior work. These studies include: (1) Agrawal and Horgan [11] for slicing programs, (2) Austin and Sohi [12] for parallelizing programs, (3) Smolens et al [20] for bounding error detection latency due to transient faults and (4) Pattabiraman et al [16] for placing error detectors to detect transient faults. To the best of our knowledge, our work is the first to utilize the DDG to infer the effects of intermittent faults on programs.…”

Section: Related Workmentioning

confidence: 99%

See 3 more Smart Citations

Modeling the Propagation of Intermittent Hardware Faults in Programs

Rashid

Pattabiraman

Gopalakrishnan

2010

2010 IEEE 16th Pacific Rim International Symposium on Dependable Computing

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Abstract-Intermittent hardware faults are bursts of errors that last from a few CPU cycles to a few seconds. Recent studies have shown that intermittent fault rates are increasing due to technology scaling and are likely to be a significant concern in future systems. We study the impact of intermittent hardware faults in programs. A simulation-based fault-injection campaign shows that the majority of the intermittent faults lead to program crashes. We build a crash model and a program model that represents the data dependencies in a fault-free execution of the program. We then use this model to glean information about when the program crashes and the extent of fault propagation. Empirical validation of our model using fault-injection experiment shows that it predicts almost all actual crash-causing intermittent faults, and in 93% of the considered faults the prediction is accurate within 100 instructions. Further, the model is found to be more than two orders of magnitude faster than equivalent fault-injection experiments performed with a microprocessor simulator.

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Section: Methodsmentioning

confidence: 99%

Section: Terms and Definitionsmentioning

confidence: 99%

Section: Computing the Intermittent Fault Propagation Setmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

See 2 more Smart Citations

Modeling the Propagation of Intermittent Hardware Faults in Programs

Rashid

Pattabiraman

Gopalakrishnan

2010

2010 IEEE 16th Pacific Rim International Symposium on Dependable Computing

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“…Dynamic techniques use information gathered during simulation or operation of the system to estimate criticality factors [18][19]. Unlike approaches based on static code analysis, dynamic analysis takes into account conditional branches, loop iterations, recursive functions, values only known in run-time, and in general, the execution progress of the application.…”

Section: Related Workmentioning

confidence: 99%

Application-Based Analysis of Register File Criticality for Reliability Assessment in Embedded Microprocessors

et al. 2015

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Abstract-There is an increasing concern to reduce the cost and overheads during the development of reliable systems. Selective protection of most critical parts of the systems represents a viable solution to obtain a high level of reliability at a fraction of the cost. In particular to design a selective fault mitigation strategy for processor-based systems, it is mandatory to identify and prioritize the most vulnerable registers in the register file as best candidates to be protected (hardened).This paper presents an application-based metric to estimate the criticality of each register from the microprocessor register file in microprocessor-based systems. The proposed metric relies on the combination of three different criteria based on common features of executed applications. The applicability and accuracy of our proposal have been evaluated in a set of applications running in different microprocessors. Results show a significant improvement in accuracy comparing to previous approaches and regardless the underlying architecture.

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A Methodology to Assess Output Vulnerability Factors for Detecting Silent Data Corruption

Duan

Tang

2019

IEEE Access

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As process technology scales, electronic devices become more susceptible to soft error induced by radiation. Silent data corruption (SDC) is considered the most severe outcome incurred by soft error. The effects of faulty variables on producing SDC vary widely. Without a profiling of vulnerability of variables, the derived detectors often incur low SDC detection rate or unacceptable overhead. To assess the vulnerability of variables to SDC, this paper proposes a metric called Output Vulnerability Factor (OVF). The metric is used to rank the variable's priority in the detector derivation process in order to selectively protect the most SDC-prone variable in the program. The calculation of OVF is based on enhanced Dynamic Dependence Graph (eDDG), a proposed instruction-level error propagation model. We filter out the edges representing the identified crash propagation path and perform a backward traversal of the eDDG to obtain SDC propagation path. Further, error masking probability is estimated for the edges refer to value comparison and logistic operation. Fault injections show that our approach achieves an SDC detection rate of 65.0% with the top 10% high OVF variables monitored. Compared with previous methods, the SDC detection rate increases by 12-21%.

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Application-Based Metrics for Strategic Placement of Detectors

Cited by 48 publications

References 13 publications

Modeling the Propagation of Intermittent Hardware Faults in Programs

Modeling the Propagation of Intermittent Hardware Faults in Programs

Application-Based Analysis of Register File Criticality for Reliability Assessment in Embedded Microprocessors

A Methodology to Assess Output Vulnerability Factors for Detecting Silent Data Corruption

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