Application-aware deadlock-free oblivious routing based on extended turn-model

Shafiee,; Zolghadr,; Arjomand,; Sarbazi-Azad,

doi:10.1109/iccad.2011.6105328

Cited by 3 publications

(3 citation statements)

References 16 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Recently, Ali [23] and Binzhang [24] proposed similar protocols called Extended Turn Model (ETM) and Abacus Turn Model (AbTM) respectively. In the AbTM routing scheme, there are two nodes specified as clockwise bead and counterclockwise bead.…”

Section: Turn Models and Degree Of Adaptivenessmentioning

confidence: 99%

“…We remove circular dependencies by deleting edges from the ICDG to generate the acyclic channel dependency graph (AICDG). Since the unpredictable arrangements of failed components break the symmetry property of a mesh network [2], we are investigating different types of generalized turn models [21], as well as AbTM [24] and ETM [23].…”

Section: Acyclic Icdg Without Virtual Channelmentioning

confidence: 99%

See 1 more Smart Citation

Fault-Aware Load-Balancing Routing for 2D-Mesh and Torus On-Chip Network Topologies

Ren

Kinsy

Zheng

2016

IEEE Trans. Comput.

View full text Add to dashboard Cite

Routing algorithm design for on-chip networks (OCNs) has become increasingly challenging due to high levels of integration and complexity of modern systems-on-chip (SoCs). The inherent unreliability of components, embedded oversized IP blocks, and fine-grained voltage-frequency islands (VFIs) management among others, raise several challenges in OCNs: (a) network topologies become irregular or asymmetric making circular route dependencies that lead to deadlock hard to detect; and (b) routing algorithms that lack strong load-balancing properties often saturate prematurely. In order to address the aforementioned deadlock and load-balancing problems, we propose the traffic balancing oblivious routing (TBOR) algorithm. It is a 2-phase routing algorithm consisting of: (1) construction of the weighted acyclic channel dependency graph (CDG) for the OCN to efficiently maximize available resource utilization; and (2) channel ordering across turn models to keep the underlying CDG cycle-free to guarantee deadlock-freedom using one or more turn-models. Channel bandwidth utilization and traffic balancing are achieved through static virtual channel allocation according to residual bandwidth of healthy links. In addition, we introduce in this work two schemes of different granularity of fault detection and analysis while guaranteeing in-order packet delivery by assigning a unique path to each flow. Extensive experiments demonstrate the proposed routing methodology outperforms previous algorithms.

show abstract

Section: Turn Models and Degree Of Adaptivenessmentioning

confidence: 99%

Section: Acyclic Icdg Without Virtual Channelmentioning

confidence: 99%

Fault-Aware Load-Balancing Routing for 2D-Mesh and Torus On-Chip Network Topologies

Ren

Kinsy

Zheng

2016

IEEE Trans. Comput.

View full text Add to dashboard Cite

show abstract

“…(2) Performance: Faults lead to a loss of path diversity in the NoC, and higher congestion for certain paths. Adaptive routing [24] [25] can mitigate some of these effects, but have to remove certain channel dependencies or prohibit certain routing paths, which reduces routing path diversity even further [26]. (3) Scalability: As we add more cores in a system, the size of the NoC grows and warrants a distributed solution since centralized solutions are not going to scale.…”

Section: Introductionmentioning

confidence: 99%

FASHION: Fault-Aware Self-Healing Intelligent On-chip Network

Ren,

Kinsy,

Zhu

et al. 2017

Preprint

View full text Add to dashboard Cite

To avoid packet loss and deadlock scenarios that arise due to faults or power gating in multicore and many-core systems, the network-onchip needs to possess resilient communication and load-balancing properties. In this work, we introduce the Fashion router, a self-monitoring and self-reconfiguring design that allows for the on-chip network to dynamically adapt to component failures. First, we introduce a distributed intelligence unit, called Self-Awareness Module (SAM), which allows the router to detect permanent component failures and build a network connectivity map. Using local information, SAM adapts to faults, guarantees connectivity and deadlock-free routing inside the maximal connected subgraph and keeps routing tables up-to-date. Next, to reconfigure network links or virtual channels around faulty/power-gated components, we add bidirectional link and unified virtual channel structure features to the Fashion router. This version of the router, named Ex-Fashion, further mitigates the negative system performance impacts, leads to larger maximal connected subgraph and sustains a relatively high degree of fault-tolerance. To support the router, we develop a fault diagnosis and recovery algorithm executed by the Built-In Self-Test, self-monitoring, and self-reconfiguration units at runtime to provide fault-tolerant system functionalities. The Fashion router places no restriction on topology, position or number of faults. It drops 54.3∼55.4% fewer nodes for same number of faults (between 30 and 60 faults) in an 8x8 2D-mesh over other state-of-the-art solutions. It is scalable and efficient. The area overheads are 2.311% and 2.659% when implemented in 8x8 and 16x16 2D-meshes using the TSMC 65nm library at 1.38GHz clock frequency.

show abstract