Application and Product-Volume-Specific Customization of BEOL Metal Pitch

Pagliarini, Samuel; Isgenc, Mehmet Meric; Martins, Mayler G. A.; Pileggi, Lawrence T.

doi:10.1109/tvlsi.2018.2828387

Cited by 8 publications

(4 citation statements)

References 10 publications

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“…Notice the significant increase in metals M5, M6, and M7. Also, note that the lower metal layers are more closely associated with the circuit performance [28], so overheads in M5 and above are unlikely to affect critical paths. We also provide a visual comparison of the density increase for the AES HFHD and PST HFHD SCTs in the bottom part of Fig.…”

Section: Sct Insertion Resultsmentioning

confidence: 99%

Hardware Trojan Insertion in Finalized Layouts: From Methodology to a Silicon Demonstration

Perez

Pagliarini

2023

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Section: Sct Insertion Resultsmentioning

confidence: 99%

Hardware Trojan Insertion in Finalized Layouts: From Methodology to a Silicon Demonstration

Perez

Pagliarini

2023

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Notice the significant increase in metals M5, M6, and M7. Also note that the lower metal layers are more closely associated with the circuit performance [26], so overheads in M5 and above are unlikely to affect critical paths. We also provide a visual comparison of the density increase for the AES HFHD and PST HFHD SCTs in the bottom part of Fig.…”

Section: Sct Insertion Resultsmentioning

confidence: 99%

Hardware Trojan Insertion in Finalized Layouts: a Silicon Demonstration

Perez¹,

Pagliarini²

2021

Preprint

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Owning a high-end semiconductor foundry is a luxury very few companies can afford. Thus, fabless design companies outsource integrated circuit fabrication to third parties. Within foundries, rogue elements may gain access to the customer's layout and perform malicious acts, including the insertion of a hardware trojan (HT). Many works focus on the structure/effects of a HT, while very few have demonstrated the viability of their HTs in silicon. Even fewer disclose how HTs are inserted or the time required for this activity. Our work details, for the first time, how effortlessly a HT can be inserted into a finalized layout by presenting an insertion framework based on the engineering change order flow. For validation, we have built an ASIC prototype in 65nm CMOS technology comprising of four trojaned cryptocores. A side-channel HT is inserted in each core with the intent of leaking the cryptokey over a power channel. Moreover, we have determined that the entire attack can be mounted in a little over one hour. We also show that the attack was successful for all tested samples. Finally, our measurements demonstrate the robustness of our SCT against skews in the manufacturing process.

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“…For a thorough discussion and silicon results on BEOL-related overheads, please refer to[18].4 VOLUME XXX, 2020…”

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confidence: 99%

A Survey on Split Manufacturing: Attacks, Defenses, and Challenges

Perez

Pagliarini

2020

IEEE Access

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In today's integrated circuit (IC) ecosystem, owning a foundry is not economically viable, and therefore most IC design houses are now working under a fabless business model. In order to overcome security concerns associated with the outsorcing of IC fabrication, the Split Manufacturing technique was proposed. In Split Manufacturing, the Front End of Line (FEOL) layers (transistors and lower metal layers) are fabricated at an untrusted high-end foundry, while the Back End of Line (BEOL) layers (higher metal layers) are manufactured at a trusted low-end foundry. This approach hides the BEOL connections from the untrusted foundry, thus preventing overproduction and piracy threats. However, many works demonstrate that BEOL connections can be derived by exploiting layout characteristics that are introduced by heuristics employed in typical floorplanning, placement, and routing algorithms. Since straightforward Split Manufacturing may not afford a desirable security level, many authors propose defense techniques to be used along with Split Manufacturing. In our survey, we present a detailed overview of the technique, the many types of attacks towards Split Manufacturing, as well as possible defense techniques described in the literature. For the attacks, we present a concise discussion on the different threat models and assumptions, while for the defenses we classify the studies into three categories: proximity perturbation, wire lifting, and layout obfuscation. The main outcome of our survey is to highlight the discrepancy between many studiessome claim netlists can be reconstructed with near perfect precision, while others claim marginal success in retrieving BEOL connections. Finally, we also discuss future trends and challenges inherent to Split Manufacturing, including the fundamental difficulty of evaluating the efficiency of the technique.

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Application and Product-Volume-Specific Customization of BEOL Metal Pitch

Cited by 8 publications

References 10 publications

Hardware Trojan Insertion in Finalized Layouts: From Methodology to a Silicon Demonstration

Hardware Trojan Insertion in Finalized Layouts: From Methodology to a Silicon Demonstration

Hardware Trojan Insertion in Finalized Layouts: a Silicon Demonstration

A Survey on Split Manufacturing: Attacks, Defenses, and Challenges

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