Applicability of a Subset of Ada as an Algorithmic Hardware Description Language for Graph-Based Hardware Compilation

Girczyc, E.F.; Buhr, R. J. A.; Knight, J.P.

doi:10.1109/tcad.1985.1270106

Cited by 29 publications

(5 citation statements)

References 3 publications

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“…The third circuit, Paulin, is an example used in [30]. The fourth circuit, oven_ctrl, is an oven control example employed in [31]. The fifth circuit, real, is an example given in [27].…”

Section: Resultsmentioning

confidence: 99%

A parameterized graph-based framework for high-level test synthesis

2006

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“…The third circuit, Paulin, is an example used in [30]. The fourth circuit, oven_ctrl, is an oven control example employed in [31]. The fifth circuit, real, is an example given in [27].…”

Section: Resultsmentioning

confidence: 99%

A parameterized graph-based framework for high-level test synthesis

2006

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“…On the contrary, list scheduling utilizes a global priority function to select the next operation to be scheduled. This global priority function can be either the mobility [1] of the operation or its urgency [2]. The mobility of an operation is the difference between its ASAP and ALAP control step in absolute terms.…”

Section: Background and Review Of Esl Methodologiesmentioning

confidence: 99%

Formal ESL Synthesis for Control-Intensive Applications

Dossis¹

2012

Advances in Software Engineering

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Due to the massive complexity of contemporary embedded applications and integrated systems, long effort has been invested in high-level synthesis (HLS) and electronic system level (ESL) methodologies to automatically produce correct implementations from high-level, abstract, and executable specifications written in program code. If the HLS transformations that are applied on the source code are formal, then the generated implementation is correct-by-construction. The focus in this work is on application-specific design, which can deliver optimal, and customized implementations, as opposed to platform or IP-based design, which is bound by the limits and constraints of the preexisting architecture. This work surveys and reviews past and current research in the area of ESL and HLS. Then, a prototype HLS compiler tool that has been developed by the author is presented, which utilizes compiler-generators and logic programming to turn the synthesis into a formal process. The scheduler PARCS and the formal compilation of the system are tested with a number of benchmarks and real-world applications. This demonstrates the usability and applicability of the presented method.

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“…On the contrary, list scheduling utilizes a global priority function to select the next operation to be scheduled. This global priority function can be either the mobility (Pangrle & Gajski, 1987) of the operation or its urgency (Girczyc et al, 1985). Force-directed scheduling calculates the range of control steps for each operation between the operation's ASAP and ALAP state assignment.…”

Section: The Scheduling Taskmentioning

confidence: 99%

High-Level Synthesis for Embedded Systems

Dossis¹

2012

Embedded Systems - Theory and Design Methodology

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Applicability of a Subset of Ada as an Algorithmic Hardware Description Language for Graph-Based Hardware Compilation

Cited by 29 publications

References 3 publications

A parameterized graph-based framework for high-level test synthesis

A parameterized graph-based framework for high-level test synthesis

Formal ESL Synthesis for Control-Intensive Applications

High-Level Synthesis for Embedded Systems

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