APPcache+: An STT-MRAM-Based Approximate Cache System With Low Power and Long Lifetime

Zhao, Wei; Feng, Dan; Tong, Wei; Liu, Jingning; Chen, Zhangyu; Wu, Bing; Wang, Chengning

doi:10.1109/tcad.2023.3267713

Cited by 3 publications

(1 citation statement)

References 42 publications

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“…A SSOCIATIVE access, i.e., access by content rather than by explicit address, is widely used across computer microarchitecture. This type of access is required for caches of all levels, translation lookahead buffers (TLB), reservation stations and register renaming in out-of-order execution engines, branch target buffers (BTB), and other fundamental microarchitectural components [1], [2], [3], [4], [5], [6], [7], [8]. Caches in typical processors are limited up to 8-way or 16-way associativity [9], [10], [11], [12], [13].…”

Section: Introductionmentioning

confidence: 99%

FASTA: Revisiting Fully Associative Memories in Computer Microarchitecture

Garzón,

Hanhan,

Lanuzza

et al. 2024

IEEE Access

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Associative access is widely used in fundamental microarchitectural components, such as caches and TLBs. However, associative (or content addressable) memories (CAMs) have been traditionally considered too large, too energy-hungry, and not scalable, and therefore, have limited use in modern computer microarchitecture. This work revisits these presumptions and proposes an energy-efficient fullyassociative tag array (FASTA) architecture, based on a novel complementary CAM (CCAM) bitcell. CCAM offers a full CMOS solution for CAM, removing the need for time-and energy-consuming precharge and combining the speed of NOR CAM and low energy consumption of NAND CAM. While providing better performance and energy consumption, CCAM features a larger area compared to state-of-the-art CAM designs. We further show how FASTA can be used to construct a novel aliasing-free, energy-efficient, Very-Many-Way Associative (VMWA) cache. Circuit-level simulations using 16 nm FinFET technology show that a 128 kB FASTA-based 256-way 8-set associative cache is 28% faster and consumes 88% less energy-per-access than a same sized 8-way (256-set) SRAM based cache, while also providing aliasingfree operation. System-level evaluation performed on the Sniper simulator shows that the VMWA cache exhibits lower Misses Per Kilo Instructions (MPKI) for the majority of benchmarks. Specifically, the 256way associative cache achieves 17.3%, 11.5%, and 1.2% lower average MPKI for L1, L2, and L3 caches, respectively, compared to a 16-way associative cache. The average IPC improvement for L1, L2, and L3 caches are 1.6%, 1.4%, and 0.2%, respectively.

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Section: Introductionmentioning

confidence: 99%

FASTA: Revisiting Fully Associative Memories in Computer Microarchitecture

Garzón,

Hanhan,

Lanuzza

et al. 2024

IEEE Access

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AmLuCEP: Amalgamating LUT-based Compression and Adaptive Encoding Assisted Block Placement To Improve Lifetime of PCM-based Main Memories

Nath,

Kapoor

2024

ACM Trans. Des. Autom. Electron. Syst.

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With the rising demands for high capacity memory and poor scalability of the existing DRAM-based main memories, the emerging Non-volatile memories captures higher attention due to their high density and low leakage power consumption. However, the possible consideration of such memories as alternatives of DRAM is largely hindered by their intrinsic drawbacks like high write latency, high write energy and low write endurance. In this paper, we propose an integrated solution by combining the effect of compression and encoding assisted block placement to improve lifetime of NVMs. We have developed a compression technique called LUT_Comp by exploiting the word-level redundancy present in the words of the incoming cache blocks to NVM. LUT_Comp remains effective in reducing bit-flips in NVMs by offering a balance in compression ratio and coverage. Additionally, we also propose an encoding based block placement policy that places the compressed blocks in the appropriate half within the memory. The integrated approach of compression and block placement termed AmLuCEP offers a uniform bit-flips distribution while further reducing bit-flips in NVM. Experimental results show that AmLuCEP reduces bit-flips by 54%, 42%, 37%, 21%; energy consumption by 41%, 28%, 24%, 13%; and improves lifetime by 57%, 40%, 38%, 21% over baseline and the existing techniques READ [38], COEF [39] and SELEC [13], respectively.

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High-efficiency and high-security emerging computing chips: development, challenges, and prospects

LIU,

CHEN,

et al. 2024

Sci. Sin.-Inf.

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APPcache+: An STT-MRAM-Based Approximate Cache System With Low Power and Long Lifetime

Cited by 3 publications

References 42 publications

FASTA: Revisiting Fully Associative Memories in Computer Microarchitecture

FASTA: Revisiting Fully Associative Memories in Computer Microarchitecture

AmLuCEP: Amalgamating LUT-based Compression and Adaptive Encoding Assisted Block Placement To Improve Lifetime of PCM-based Main Memories

High-efficiency and high-security emerging computing chips: development, challenges, and prospects

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