APOLLO: An Automated Power Modeling Framework for Runtime Power Introspection in High-Volume Commercial Microprocessors

Xie, Zhiyao; Xu, Xiaoqing; Walker, M.; Knebel, Joshua; Palaniswamy, Kumaraguru; Hebert, Nicolas; Hu, Jiang; Yang, Huanrui; Chen, Yiran; Das, Shidhartha

doi:10.1145/3466752.3480064

Cited by 15 publications

(11 citation statements)

References 51 publications

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“…Since each module in the processor rarely exceeds eight cycles, we believe that the interval of 8-cycle will achieve the best results. Our observations can also be corroborated by [4], the accuracy of APOLLO τ (τ =8) is better than APOLLO and APOLLO τ (τ =T). So we cut the original waveform record into 8-cycle segments and used the sum of signal changes within each segment as the signal trace.…”

Section: Purification Of Training Tracesupporting

confidence: 84%

“…This kind of work gets the power label through power simulation tools. It obtains circuit signal transformations per cycle through waveform change files, then uses a feature selection method to select suitable circuit signals to build the power model [3], [4], [5], [6]. Signal-proxy methods are usually used in FPGA-based power simulators and can potentially be used to detect voltage droop online.…”

Section: Signal-proxy Approachesmentioning

confidence: 99%

“…Like APOLLO [4], we adopt the pruning and relaxation process to select proxies. We use Positive-Defined lasso(PD-lasso) to take on the role of pruning and linear regression for relaxation.…”

Section: Selection Of Proxymentioning

confidence: 99%

“…After filtering out the appropriate proxies, we use a linear regression method to obtain more precise weights. Table 2 com Like APOLLO [4], the toggle detection has three cases:…”

Section: Selection Of Proxymentioning

confidence: 99%

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Lightweight Online Power Estimation Methodology via Power Abstract Counters

Fan¹,

Zhang²

2022

Preprint

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<p>Performance Monitor Counter(PMC)-based and circuit signal-based approaches are the two primary methodologies for online power estimation of processors. PMC-based methods will not bring hardware overhead, but the observation granularity is too large to be applied to fine-grained power management strategies. Meanwhile, signal-based methods bring high hardware overhead, and current power management strategies cannot effectively utilize clock-level precision. In this paper, we propose Power Abstract Counter(PAC). This counter records the change times of circuit signal closely related to the processor's power consumption. We also developed an online power estimation method based on PAC. This method combines the advantages of PMC-based and signal-based methods. It can estimate the processor's power at a smaller observation granularity and has a low hardware overhead. We validate the approach on the Loongson GS364 processor. The results show that using 16 PACs can achieve an estimation error of less than 1% within a granularity of 512 cycles.</p>

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Section: Purification Of Training Tracesupporting

confidence: 84%

Section: Signal-proxy Approachesmentioning

confidence: 99%

Section: Selection Of Proxymentioning

confidence: 99%

“…After filtering out the appropriate proxies, we use a linear regression method to obtain more precise weights. Table 2 com Like APOLLO [4], the toggle detection has three cases:…”

Section: Selection Of Proxymentioning

confidence: 99%

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Lightweight Online Power Estimation Methodology via Power Abstract Counters

Fan¹,

Zhang²

2022

Preprint

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“…Pyramid [22] proposed a machine learning framework that estimates the resource usage of an HLS design where they tested and compared the prediction accuracies of many ML models including Linear Regression, ANNs, Supporting Vector Machines (SVMs), and Random Forests. Apollo [39] designed a linear model to model the power of a microprocessor executing different workloads with an 𝑅 2 >0.95 accuracy and showed that the simulation time was reduced from months to minutes.…”

Section: Related Workmentioning

confidence: 99%

SNS's not a synthesizer

Kjellqvist

Wills

2022

Proceedings of the 49th Annual International Symposium on Computer Architecture

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The number of transistors that can fit on one monolithic chip has reached billions to tens of billions in this decade thanks to Moore's Law. With the advancement of every technology generation, the transistor counts per chip grow at a pace that brings about exponential increase in design time, including the synthesis process used to perform design space explorations. Such a long delay in obtaining synthesis results hinders an efficient chip development process, significantly impacting time-to-market. In addition, these large-scale integrated circuits tend to have larger and higher-dimension design spaces to explore, making it prohibitively expensive to obtain physical characteristics of all possible designs using traditional synthesis tools.In this work, we propose a deep-learning-based synthesis predictor called SNS (SNS's not a Synthesizer), that predicts the area, power, and timing physical characteristics of a broad range of designs at two to three orders of magnitude faster than the Synopsys Design Compiler while providing on average a 0.4998 RRSE (root relative square error). We further evaluate SNS via two representative case studies, a general-purpose out-of-order CPU case study using RISC-V Boom open-source design and an accelerator case study using an in-house Chisel implementation of DianNao, to demonstrate the capabilities and validity of SNS. CCS CONCEPTS• Hardware → Integrated circuits; High-level and registertransfer level synthesis; • Computing methodologies → Neural networks.

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