ApGAN: Approximate GAN for Robust Low Energy Learning From Imprecise Components

Roohi, Arman; Sheikhfaal, Shadi; Angizi, Shaahin; Fan, Deliang; DeMara, Ronald F.

doi:10.1109/tc.2019.2949042

Cited by 24 publications

(11 citation statements)

References 24 publications

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“…Roohi et al [45] Proposes approximate GAN architecture to get optimization in both hardware and software using quantization to reduce computation. The approximation is also applied for deconv layers to avoid zeros for fractional strides.…”

Section: State-of-the-art Hardware Architectures For Generative Adver...mentioning

confidence: 99%

“…The non-volatile memory technique exerts interesting features such as compatibility and high density integration. Roohi et al proposed a processing-in-memory based GAN architecture ApGAN or approximate generative adversarial network for optimization in both software and hardware perspective [45]. In ApGAN, the architecture is designed for resource-limited environment, where both the hardware and software are optimized in order to minimize the overhead.…”

Section: State-of-the-art Hardware Architectures For Generative Adver...mentioning

confidence: 99%

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From DNNs to GANs: Review of efficient hardware architectures for deep learning

Bhattacharya¹

2021

Preprint

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In recent times, the trend in very large scale integration (VLSI) industry is multi-dimensional, e.g. reduction of energy consumption, occupancy of less space, precise result, less power dissipation, faster response etc. To meet these needs, the hardware architecture should be reliable and robust to these problems. Recently, neural network and deep learning has been started to impact the present research paradigm significantly which consists of parameters in the order of millions, nonlinear function for activation, convolutional operation for feature extraction, softmax regression for classification, generative adversarial networks, etc. These operations involve huge calculation and memory overhead. Presently available DSP processors are incapable of performing these operations and they most face the problems e.g. memory overhead, performance drop and compromised accuracy. Moreover, if a huge silicon area is powered to accelerate the operation using parallel computation, the IC's will be having significant chance of burning out due to the considerable generation of heat. Hence, novel dark silicon constraint is developed to reduce the heat dissipation without sacrificing the accuracy. Similarly, different algorithms have been adapted to design a DSP processor compatible for fast performance in neural network, activation function, convolutional neural network and generative adversarial network. In this review, we illustrate the recent developments in hardware for accelerating the efficient implementation of deep learning networks with enhanced performance. The techniques investigated in this review are expected to direct future research challenges of hardware optimization for high-performance computations.

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Section: State-of-the-art Hardware Architectures For Generative Adver...mentioning

confidence: 99%

Section: State-of-the-art Hardware Architectures For Generative Adver...mentioning

confidence: 99%

From DNNs to GANs: Review of efficient hardware architectures for deep learning

Bhattacharya¹

2021

Preprint

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“…In [17], the memory array has been modified, including up to 4 memristors arranged in parallel in the same cell, in order to have multiple resistance values and so higher precision weights. Based on a similar approach to [12], a GAN training accelerator has been discussed in [18] which is able to efficiently perform approximated add/sub operations in a memristor array, achieving both speed-up and high energy efficiency. 3.…”

Section: A Quick Overviewmentioning

confidence: 99%

“…Some of them are considering the binary approximations, choosing an implementation based on emerging technologies. Some works [12,13,26,27] are based on MTJ technology while [15][16][17][18]28,29] have used RRAM. In each of these works the resistive element is used to perform simple logical operations based on current sensing technique.…”

Section: Nn Implementations Based On Lim Conceptmentioning

confidence: 99%

Logic-in-Memory Computation: Is It Worth It? A Binary Neural Network Case Study

Coluccio

Vacca

Turvani

2020

JLPEA

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Recently, the Logic-in-Memory (LiM) concept has been widely studied in the literature. This paradigm represents one of the most efficient ways to solve the limitations of a Von Neumann’s architecture: by placing simple logic circuits inside or near a memory element, it is possible to obtain a local computation without the need to fetch data from the main memory. Although this concept introduces a lot of advantages from a theoretical point of view, its implementation could introduce an increasing complexity overhead of the memory itself, leading to a more sophisticated design flow. As a case study, Binary Neural Networks (BNNs) have been chosen. BNNs binarize both weights and inputs, transforming multiply-and-accumulate into a simpler bitwise logical operation while maintaining high accuracy, making them well-suited for a LiM implementation. In this paper, we present two circuits implementing a BNN model in CMOS technology. The first one, called Out-Of-Memory (OOM) architecture, is implemented following a standard Von Neumann structure. The same architecture was redesigned to adapt the critical part of the algorithm for a modified memory, which is also capable of executing logic calculations. By comparing both OOM and LiM architectures we aim to evaluate if Logic-in-Memory paradigm is worth it. The results highlight that LiM architectures have a clear advantage over Von Neumann architectures, allowing a reduction in energy consumption while increasing the overall speed of the circuit.

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“…In the last two decades, Processing-in-Memory (PIM) architecture, as a potentially viable way to solve the memory wall challenge, has been well explored for different applications [5], [6], [7], [8], [9], [10], [11]. Especially processing-in-non-volatile memory architecture has achieved remarkable success by dramatically reducing data transfer energy and latency [12], [13], [14], [15], [16]. The key concept behind PIM is to realize logic computation within memory to process data by leveraging the inherent parallel computing mechanism and exploiting large internal memory bandwidth.…”

Section: Introductionmentioning

confidence: 99%

PANDA: Processing-in-MRAM Accelerated De Bruijn Graph based DNA Assembly

Angizi¹,

Fahmi²,

Zhang³

et al. 2020

Preprint

Self Cite

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Spurred by widening gap between data processing speed and data communication speed in Von-Neumann computing architectures, some bioinformatic applications have harnessed the computational power of Processing-in-Memory (PIM) platforms. However, the performance of PIMs unavoidably diminishes when dealing with such complex applications seeking bulk bit-wise comparison or addition operations. In this work, we present an efficient Processing-in-MRAM Accelerated De Bruijn Graph based DNA Assembly platform named PANDA based on an optimized and hardware-friendly genome assembly algorithm. PANDA is able to assemble large-scale DNA sequence data-set from all-pair overlaps. We first design PANDA platform that exploits MRAM as a computational memory and converts it to a potent processing unit for genome assembly. PANDA can execute not only efficient bulk bit-wise X(N)ORbased comparison/addition operations heavily required for the genome assembly task but a full-set of 2-/3-input logic operations inside MRAM chip. We then develop a highly parallel and stepby-step hardware-friendly DNA assembly algorithm for PANDA that only requires the developed in-memory logic operations. The platform is then configured with a novel data partitioning and mapping technique that provides local storage and processing to fully utilize the algorithm-level's parallelism. The cross-layer simulation results demonstrate that PANDA reduces the run time and power, respectively, by a factor of 18 and 11 compared with CPU. Besides, speed-ups of up-to 2-4× can be obtained over recent processing-in-MRAM platforms to perform the same task.

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ApGAN: Approximate GAN for Robust Low Energy Learning From Imprecise Components

Cited by 24 publications

References 24 publications

From DNNs to GANs: Review of efficient hardware architectures for deep learning

From DNNs to GANs: Review of efficient hardware architectures for deep learning

Logic-in-Memory Computation: Is It Worth It? A Binary Neural Network Case Study

PANDA: Processing-in-MRAM Accelerated De Bruijn Graph based DNA Assembly

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