Anomalous B penetration through ultrathin gate oxides during rapid thermal annealing

Fair, Richard B.

doi:10.1109/55.784454

Cited by 11 publications

(8 citation statements)

References 13 publications

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“…R.B. Fair especially discusses the role of both fluorine and optical illumination on the diffusion of boron in SiO [34], although not specifically in silicon. Because of these important differences, it is difficult to draw definitive conclusions on the role that optical radiation (or the lack thereof) plays during microwave annealing.…”

Section: Usj Resultsmentioning

confidence: 99%

Electromagnetic fast firing for ultrashallow junction formation

Thompson

Booske

Cooper

et al. 2003

IEEE Trans. Semicond. Manufact.

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Abstract-The creation of low resistivity, ultrashallow source/drain regions in MOS device structures requires rapid thermal processing (RTP) techniques that restrict diffusion and activate a significant percentage of the implanted dopant species. While current heating techniques depend upon illumination based heating, a new technology, electromagnetic induction heating (EMIH), achieves a rapid heating of the silicon by coupling electromagnetic radiation directly into the silicon wafer. Heating rates of 125 C s to temperatures in excess of 1050 C have been achieved for 75-and 100-mm-diameter wafers at input powers of 1000 and 1300 W, respectively. These ramp rates are suitable for ultrashallow junction formation, and junctions shallower than 30 nm with sheet resistances lower than 600 /square have been achieved. This paper details the application of electromagnetic heating using radiation in the microwave, 2450 MHz, frequency regime. Experimental results, comparing microwave annealed implants to the well documented SEMATECH requirements, and simulations, utilizing a coupled electromagnetic-thermal computer model, of the heating process are discussed.

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Section: Usj Resultsmentioning

confidence: 99%

Electromagnetic fast firing for ultrashallow junction formation

Thompson

Booske

Cooper

et al. 2003

IEEE Trans. Semicond. Manufact.

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“…In particular, there is conflicting evidence concerning the ability of a surface or interface to absorb interstitials of Si, boron, phosphorus, and related elements. 42,44 On the other hand, Napolitani et al 45 have cited low levels of boron dose loss compared to phosphorus in order to claim that the interface acts as a poor sink for B i . During annealing, an interface of Si/ SiO 2 typically overlies the diffusing profile.…”

Section: B Evaluation Of Smentioning

confidence: 99%

A method for quantifying annihilation rates of bulk point defects at surfaces

Kwok

Dev

Braatz

et al. 2005

Journal of Applied Physics

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High-temperature real-time observation of surface defects induced by single ion irradiation using scanningtunneling-microscope/ion-gun combined system Point defects such as vacancies and interstitial atoms serve as primary mediators of solid-state diffusion in many materials. In some cases, the defects encounter surfaces where annihilation can occur. Quantification of annihilation rates presents formidable challenges, since point defect concentrations are typically low and therefore difficult to monitor directly. The present work develops a method for such quantification based upon measurements of diffusional profile spreading of a foreign species, using as an example isotopically labeled silicon implanted into a silicon matrix. Optimal experimental design techniques together with maximum-likelihood estimation indicate that the loss probability for Si interstitials on nitrogen-covered Si͑100͒ lies at 7.1ϫ 10 −4 .

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“…Many works demonstrated the major interest of EOT reduction to improve drive current without damage off-channel one's [1]. However, it has been established that two major issues are limiting gate oxide reduction way: boron penetration inside p-channel during dopants activation [2] [3] and gate oxide leakage [4] [5]. A solution, to moderate simultaneously boron diffusion and gate leakage, is to use an oxynitride for gate oxide material [4].…”

Section: Qwurgxfwlrqmentioning

confidence: 99%

Gate Oxide Process Impact on RNCE for Advanced CMOS Transistors

Arnaud

Bidaud

2002

32nd European Solid-State Device Research Conference

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670LFURHOHWURQLFV UXH -0RQHW &UROOHV )UDQFH IUDQFNDUQDXG#VWFRP M. Bidaud 3KLOLSV 6HPLFRQGXFRUV UXH -0RQHW &UROOHV )UDQFH $EVWUDFW 7KLV SDSHU SUHVHQWV WKH VXEVWDQWLDO LPSDFW RI JDWH R[LGH SURFHVV RQ WKH 5HYHUVH 1DUURZ &KDQQHO (IIHFW 51&( :H FRPSDUHG WKH ZLGWKGHSHQGHQFLHV RI 1 FKDQQHO WUDQVLVWRU LQ FDVH RI SXUH R[LGH SURFHVV DQG R[\QLWULGH SURFHVV XVLQJ HLWKHU 5DSLG 7KHUPDO 1LWULGDWLRQ 571 RU 'HFRXSOHG 3ODVPD 3URFHVV '31 7KH UROH RI R[LGDWLRQ SRZHU WR UDLVH WKH 51&( KDV EHHQ GHPRQVWUDWHG E\ ERG\ IDFWRU PHDVXUHPHQWV $Q HPSLULFDO PRGHO ZDV HVWDEOLVKHG WR H[WUDFW WKH 6KDOORZ 7UHQFK ,VRODWLRQ 67, HGJH FXUUHQW FRPSRQHQW $FWLYDWLRQ HQHUJ\ RI 67,HGJH OHDNDJH ZDV ZRUNHG RXW IRU HDFK JDWH R[LGH SURFHVV )LQDOO\ ZH GHPRQVWUDWHG WKH VWURQJ LQWHUHVW RI QLWULGDWLRQ PHWKRG WR OLPLW SDUDVLWLF 51&( ,QWURGXFWLRQ To enhance the sub-0.1µm transistor performance, aggressive Equivalent Oxide Thickness (EOT) was used for gate oxide. Many works demonstrated the major interest of EOT reduction to improve drive current without damage off-channel one's [1]. However, it has been established that two major issues are limiting gate oxide reduction way: boron penetration inside p-channel during dopants activation [2] [3] and gate oxide leakage [4] [5]. A solution, to moderate simultaneously boron diffusion and gate leakage, is to use an oxynitride for gate oxide material [4]. Several papers exhibit the dangers of gate nitridation option, especially in term of gate oxide integrity and carriers mobility degradation [6]. On our side, we investigated another phenomena induced by oxidizing process: the dopant segregation inducing threshold voltage (V th ) roll-down for narrowest transistors. This work is focused on the strong impact of gate oxide process on narrow width effect due to the acceptors ions segregation inside STI-oxide during the gate oxidation step. ([SHULPHQWDO A standard CMOS process was performed on <100> Si-bulk substrate, including conventional STI, dual gate oxide and cobalt salicide process. Source-drain extensions were built with low energy Arsenic implantation and high dose (1e15at/cm²). Dopants were activated during a rapid anneal at 1025°C. Table 1 supplies the details of gate oxide trials performed for these experiments. Table1: summary of gate oxide experiments 3URFHVV LG 3URFHVV IHDWXUHV (27 QP >1@ RTO (pure oxide) RTO 900°C 2.0 0 RTO+RTN RTO 900°C RTN 950°C 1.8 4 RTO+DPN RTO 900°C DPN 35" 1.65 8 RTO+DPN+Anneal RTO 900°C DPN 35" Anneal 1000°/15" 1.8 10 RTN+DPN+Anneal RTN 950°C DPN 35" Anneal 1000°/15" 1.6 14A pure oxide, as reference, was realized with Rapid Thermal Oxidation (RTO). All the recipes used RTO as a pre-oxide before an additional nitridation step performed either with RTN or DPN method. Nitridation process used NO gas. Only last trial did not have a pre-oxide option, and used a direct nitridation mode in RTN coupled with a DPN. Table 1 explains main process conditions as temperature and time. The EOT have been extracted from C-V curves after fitting with simulated plot using Schrödinger-Poisson method [7]. The ...

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Anomalous B penetration through ultrathin gate oxides during rapid thermal annealing

Cited by 11 publications

References 13 publications

Electromagnetic fast firing for ultrashallow junction formation

Electromagnetic fast firing for ultrashallow junction formation

A method for quantifying annihilation rates of bulk point defects at surfaces

Gate Oxide Process Impact on RNCE for Advanced CMOS Transistors

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