Annealing Process on Metal–Oxide–Semiconductor Channel Properties for Quasivertical GaN‐on‐Sapphire Trench Metal–Oxide–Semiconductor Field‐Effect Transistor

Abstract

Quasi‐vertical GaN trench‐gate MOSFETs with different etch RF power and the impact of the order of annealing process in TMAH wet treatment have been fabricated and studied. The high‐power device has a threshold voltage of 5.3 V and a maximum saturation current density of 552 A/cm2, whereas the low‐power device has a threshold voltage of 4.5 V and a maximum saturation current density of 650 A/cm2. However, the low‐power device has more severe off‐state leakage due to more fixed charges and defects on the device surface. Furthermore, the annealing process serves as an additional step before wet treatment. SEM image indicates that annealing at high temperatures prior to etching can eliminate surface oxide and redistribute surface imperfections, resulting in a smoother sidewall morphology. The relationship between temperature and mobility confirms the impact of the crystal surface feature on device performance.This article is protected by copyright. All rights reserved.