Analyzing the Intel Itanium Memory Ordering Rules Using Logic Programming and SAT

Yang, Yue; Gopalakrishnan, Ganesh; Lindstrom, Gary; Slind, Konrad

doi:10.1007/978-3-540-39724-3_9

Cited by 24 publications

(24 citation statements)

References 12 publications

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“…Many studies describe tools for testing litmus tests on a formally specified memory model [10,20,21,23,24]. Given a parallel program and an expected outcome, these tools report whether the specified outcome is feasible on a specified memory model.…”

Section: Related Workmentioning

confidence: 99%

“…An execution of a concurrent program is sequentially consistent if all reads and writes appear to have occurred in a sequential order that is in agreement with the individual program orders of each thread. In order to improve system performance and allow common hardware optimization techniques such as store buffers, many systems implement weaker memory models such as SPARC's TSO, PSO and RMO [22], Intel's x86 [15], Intel's Itanium [24], ARM and PowerPC [2].…”

Section: Introductionmentioning

confidence: 99%

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Generating Litmus Tests for Contrasting Memory Consistency Models

Mador-Haim

Alur

Martin

2010

Computer Aided Verification

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Abstract. Well-defined memory consistency models are necessary for writing correct parallel software. Developing and understanding formal specifications of hardware memory models is a challenge due to the subtle differences in allowed reorderings and different specification styles. To facilitate exploration of memory model specifications, we have developed a technique for systematically comparing hardware memory models specified using both operational and axiomatic styles. Given two specifications, our approach generates all possible multi-threaded programs up to a specified bound, and for each such program, checks if one of the models can lead to an observable behavior not possible in the other model. When the models differs, the tool finds a minimal "litmus test" program that demonstrates the difference. A number of optimizations reduce the number of programs that need to be examined. Our prototype implementation has successfully compared both axiomatic and operational specifications of six different hardware memory models. We describe two case studies: (1) development of a non-store atomic variant of an existing memory model, which illustrates the use of the tool while developing a new memory model, and (2) identification of a subtle specification mistake in a recently published axiomatic specification of TSO.

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Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Generating Litmus Tests for Contrasting Memory Consistency Models

Mador-Haim

Alur

Martin

2010

Computer Aided Verification

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“…Excerpts from the Itanium Ordering Rules (For the full spec, see [18]) t0 t1 t2 t3 For example, consider the tuples with id=0, id=1, and id=2. These are tuples coming from the store instruction of P0 (proc=0), have program counter pc=0, employ variable var=0, and have data=1.…”

Section: Overview Of Our Approachmentioning

confidence: 99%

“…This is to facilitate modeling the the semantics of load bypassing-the ability of a processor to read its own store early. For details, please see [2,18]. The modeling details associated with load instructions are much simpler.…”

Section: Overview Of Our Approachmentioning

confidence: 99%

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QB or Not QB: An Efficient Execution Verification Tool for Memory Orderings

Gopalakrishnan

Yang

Sivaraj

2004

Computer Aided Verification

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Abstract. We study the problem of formally verifying shared memory multiprocessor executions against memory consistency models-an important step during post-silicon verification of multiprocessor machines. We employ our previously reported style of writing formal specifications for shared memory models in higher order logic (HOL), obtaining intuitive as well as modular specifications. Our specification consists of a conjunction of rules that constrain the global visibility order. Given an execution to be checked, our algorithm generates Boolean constraints that capture the conditions under which the execution is legal under the visibility order. We initially took the approach of specializing the memory model HOL axioms into equivalent (for the execution to be checked) quantified boolean formulae (QBF). As this technique proved inefficient, we took the alternative approach of converting the HOL axioms into a program that generates a SAT instance when run on an execution. In effect, the quantifications in our memory model specification were realized as iterations in the program. The generated Boolean constraints are satisfiable if and only if the given execution is legal under the memory model. We evaluate two different approaches to encode the Boolean constraints, and also incremental techniques to generate and solve Boolean constraints. Key results include a demonstration that we can handle executions of realistic lengths for the modern Intel Itanium memory model. Further research into proper selection of Boolean encodings, incremental SAT checking, efficient handling of transitivity, and the generation of unsatisfiable cores for locating errors are expected to make our technique practical.

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UMM: an operational memory model specification framework with integrated model checking capability

Yang

Gopalakrishnan

Lindstrom

2005

Concurrency and Computation

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SUMMARYGiven the complicated nature of modern shared memory systems, it is vital to have a systematic approach to specifying and analyzing memory consistency requirements. In this paper, we present the UMM specification framework, which integrates two key features to support memory model verification: (i) it employs a simple and generic memory abstraction that can capture a large collection of memory models as guarded commands with a uniform notation, and (ii) it provides built-in model checking capability to enable formal reasoning about thread behaviors. Using this framework, memory models can be specified in a parameterized style-designers can simply redefine a few bypassing rules and visibility ordering rules to obtain an executable specification of another memory model. We formalize several classical memory models, including Sequential Consistency, Coherence, and PRAM, to illustrate the general techniques of applying this framework. We then provide an alternative specification of the Java memory model, based on a proposal from Manson and Pugh, and demonstrate how to analyze Java thread semantics using model checking. We also compare our operational specification style with axiomatic specification styles and explore a mechanism that converts a memory model definition from one style to the other.

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Analyzing the Intel Itanium Memory Ordering Rules Using Logic Programming and SAT

Cited by 24 publications

References 12 publications

Generating Litmus Tests for Contrasting Memory Consistency Models

Generating Litmus Tests for Contrasting Memory Consistency Models

QB or Not QB: An Efficient Execution Verification Tool for Memory Orderings

UMM: an operational memory model specification framework with integrated model checking capability

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