Analyzing preemptive fixed priority scheduling of data flow graphs

Abstract

Data flow graphs can conveniently model embedded streaming applications (ESAs) that are typically implemented as networks of concurrent tasks having an iterative pipelined execution, where the activation of each task may be conditioned by intra-and inter-iteration data dependencies. We propose a novel analysis approach for preemptive Fixed Priority Scheduling (FPS) of multiple ESAs assuming a fixed mapping of tasks onto the processors of the underlying Heterogeneous Multi-Processor System-on-Chip (HMPSoC).The tasks of an ESA are event activated, have varying execution times, and participate in cyclic dependency chains such that they may not have an activation pattern that can be depicted using traditional periodic / sporadic event models. Instead we propose to characterize the data flow graphs of ESAs to upper bound the load they impose on a processor and use it to compute the worst-case response time of an actor executing on that processor at a lower priority. We show that ours is a generic approach for analyzing FPS of data flow graphs. We also propose a refinement of our technique for graphs with a dominant periodic source. We demonstrate our improvement over the state-of-theart FPS analysis for data flow in our experiments.

State-based real-time analysis of SDF applications on MPSoCs with shared communication resources

“…Recently, the work of Hausman et al [27] and Lele et al [28] address extending above data flow based systems to support non starvation-free scheduling particularly preemptive fixed-priority scheduling.…”

Towards State-Based RT Analysis of FSM-SADFGs on MPSoCs with Shared Memory Communication

“…Utilizing purely analytical approaches to obtain upper and lower timing bound of dataflow applications execution time is a wide spread research topic. Closest to our research are [12,9,11,2]. While such approaches are fast and able to handle large systems, unfortunately they deliver pessimistic results especially when handling state-based bus arbitration protocols typically used in Multi-Processor Systems on a Chip (MPSoCs).…”