Analyzing N-Curve Metrics for Sub-Threshold 65nm CMOS SRAM

Samson, Mamatha; Srinivas, M.B.

doi:10.1109/nano.2008.16

Cited by 15 publications

(7 citation statements)

References 4 publications

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“…In this method, two different circuits are required to obtain the read SNM and write SNM. In N-curve method [15]- [18], SNM in both read and write modes can be obtained at a time. Butterfly curves of basic 6T SRAM cell and proposed SRAM cell are depicted in Figures 8 and 9 respectively.…”

Section: Stability Analysismentioning

confidence: 99%

Ultra-low leakage static random access memory design

Anitha

Ahmad²

2023

IJRES

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An ultra-low leakage static random-access memory (SRAM) cell structure with 8 transistors is proposed in this paper. Compared to the 6T SRAM and other existing 8T SRAM cells, leakage power of the proposed cell in hold mode reduced significantly. The stability parameters of the proposed cell are calculated using butterfly method and also N-curve method. Proposed SRAM achieves better write margin with slightly less read margin than 6T SRAM. Proposed technique consumes 790 PW of power in hold mode, which is very less compared to other existing techniques. Therefore, the proposed cell is appropriate for hold mode applications. The simulations are carried out by using Cadence (Virtuoso Schematic and layout editor) tools with GPDK45-nm technology.

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Section: Stability Analysismentioning

confidence: 99%

Ultra-low leakage static random access memory design

Anitha

Ahmad²

2023

IJRES

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“…It can be understood as, SVNM and SINM gives the read stability of 6-T SRAM cell simultaneously WTV and WTI provides the information for write ability of SARAM. Higher the static noise power margin (SPNM=SINM * SVNM), higher is the read stability and lower the write trip power (WTP=WTI * WTV), higher is the write ability of the cell [35]. 6 T SRAM cell is simulated to obtain N curves for various cell ratio (CR=0.5→2) and pull up ratio (PR=0.5→2) in order to analyze the read stability and write ability.…”

Section: Read Stability and Write Ability Analysis Of 6-t Sram Cellmentioning

confidence: 99%

“…This is due to the fact that after point B the sign of the current changes. The voltage difference between the points A and B is termed as static voltage noise margin (SVNM) [35,36].…”

Section: Read Stability and Write Ability Analysis Of 6-t Sram Cellmentioning

confidence: 99%

Performance evaluation of double gate tunnel FET based chain of inverters and 6-T SRAM cell

Kumar

2019

Eng. Res. Express

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In this work, a Lookup table based verilog-A model is employed in cadence to evaluate the performance of the chain of inverters and 6-T SRAM cell based on double gate Tunnel-field-effect transistor (DGTFET). In order to drive large capacitance with fixed number of inverters stages with constant width of N type DGTFET (W n ), it is found that the time delay performance of the inverter chain depends on the ratio of width of P type DGTFET of nth stage (Wp n ) to width of P type DGTFET of n-1th stage (Wp n−1 ). Simulation results investigated that the time delay is minimized to 0.265 ns for Wp n /Wp n−1 =3. The impact of cell ratio (CR) and pull up ratio (PR) on the read stability and write ability of 6-T SRAM cell are investigated by using N curve simulations. It is observed that, increasing CR and PR strengthens the read stability and degrades the write ability of 6-T SRAM cell.

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“…It is given by the voltage between the second "B" and last zero crossing point "C". Write Trip Current (WTI) is defined as the amount of current need to write the cell when both bit lines are clamped at [15]. The peak value of after the second zero crossing of N-curve gives WTI.…”

Section: Fig 5: N-curve Of the Sram Cellmentioning

confidence: 99%

8T SRAM Cell Design for Dynamic and Leakage Power Reduction

Gopal¹,

Prasad²,

Raj³

2013

IJCA

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This paper addresses a, novel eight transistor (8T) CMOS SRAM cell design to enhance the stability and to reduce dynamic and leakage power. For the validation of proposed 8T SRAM cell, compared results with reported data. The parameters used in the proposed cell are comparable to the existing 8T SRAM cell at same technology and design rules. The stability of the proposed cell has been analyzed using N-curve metrics. Write operation is achieved in the proposed 8T SRAM cell by charging / discharging single Bit Line (BL), which results in reduction of dynamic power consumption. The proposed 8T SRAM cell has achieved 38.33% dynamic power reduction and 25.31% reduction in leakage power comparing with the reported data of 8T SRAM cell, which validate the desired design approach.

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Analyzing N-Curve Metrics for Sub-Threshold 65nm CMOS SRAM

Cited by 15 publications

References 4 publications

Ultra-low leakage static random access memory design

Ultra-low leakage static random access memory design

Performance evaluation of double gate tunnel FET based chain of inverters and 6-T SRAM cell

8T SRAM Cell Design for Dynamic and Leakage Power Reduction

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