Analyzing memory accesses with modern processors

Noll, Stefan; Teubner, Jens; May, Norman; Böhm, Alexander

doi:10.1145/3399666.3399896

Cited by 2 publications

(3 citation statements)

References 26 publications

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“…Hotspot and vTune also offer an interactive view to zoom in on function-specific profiles or time intervals, also by selecting hardware events of interest. Furthermore, there are profilers built to analyze specific events (e.g., Intel's PIN monitors memory bandwidth usage), while Noll et al visualize memory access patterns [21,28,35].…”

Section: Related Workmentioning

confidence: 99%

“…Profiling (compiling) dataflow systems has always been a non-trivial task. Prior work includes manual analysis of profile components to attribute samples to operators [35], replaying execution in a simulator [48], tracking memory allocations to map samples to data-structures [41], call-stack sampling within the Java virtual machine [45], or dynamic calling contexts to reduce overhead of call-stack sampling [6]. All of these approaches, however, fall short of providing a universal operator mapping that works for any abstraction level and can at the same time be sampled with low overhead and sufficient frequency to show behavior over time.…”

Section: Related Workmentioning

confidence: 99%

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Profiling dataflow systems on multiple abstraction levels

Beischl

Kersten

Bandle

et al. 2021

Proceedings of the Sixteenth European Conference on Computer Systems

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Dataflow graphs are a popular abstraction for describing computation, used in many systems for high-level optimization. For execution, dataflow graphs are lowered and optimized through layers of program representations down to machine instructions. Unfortunately, performance profiling such systems is cumbersome, as today's profilers present results merely at instruction and function granularity. This obfuscates the connection between profiles and high-level constructs, such as operators and pipelines, making interpretation of profiles an exercise in puzzling and deduction.In this paper, we show how to profile compiling dataflow systems at higher abstraction levels. Our approach tracks the code generation process and aggregates profiling data to any abstraction level. This bridges the semantic gap to match the engineer's current information need and even creates a comprehensible way to report timing information within profiling data. We have evaluated this approach within our compiling DBMS Umbra, showing that the approach is generally applicable for compiling dataflow systems and can be implemented with high accuracy and reasonable overhead.CCS Concepts: • Software and its engineering → Data flow architectures.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Profiling dataflow systems on multiple abstraction levels

Beischl

Kersten

Bandle

et al. 2021

Proceedings of the Sixteenth European Conference on Computer Systems

View full text Add to dashboard Cite

show abstract

“…However, pointer chaining is truly limited for memory access latency. [27], [32], [67] researched approaches using hardware-based memory traces and software-based prefetching, which all improved the memory access performance. In addition, hardware transactional memory (HTM) based on cache coherence has been studied in many works [68]-[71].…”

Section: Related Workmentioning

confidence: 99%

A Performance Evaluation of DRAM Access for In-Memory Databases

et al. 2021

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The latest CPUs(computer cpu processors) employ multiple cores, massively superscalar pipelines, out-of-order execution of tons of instructions, and advanced SIMD capabilities, which can hide the memory access latency. And most of recent memory-oriented data structures have already benefit from these features. However, due to the complexity of data organization, these CPUs do not always work well in memory resident database systems (MMDBs), particularly regarding storing data in dynamic randomaccess memory (DRAM). This article studies memory-efficient data structures by analyzing the run time, access latency, cache misses, instructions per cycle (IPC), and DRAM reads (bytes). Then, we design and implement two data organization schemas in the main memory database: dispersing data block organization and clustering data block organization. Using algorithmic engineering and careful attention to internal parallelism, cache alignment can hide the memory access latency. However, we find that these data structures work well in some cases, though they have been eclipsed in the face of complex access paths. To determine the reasons, we study the impact of database techniques on memory access latency, such as data partitioning, storage models, and by processing algorithms. With the specific main memory database system, we estimate the performance of each data organization schema based on DRAM DDR4 and the latest Intel Haswell microarchitecture. In conclusion, this work will make DRAM access applicable in real-world situations by implementing the schema to systems, such as in-memory databases.

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Analyzing memory accesses with modern processors

Cited by 2 publications

References 26 publications

Profiling dataflow systems on multiple abstraction levels

Profiling dataflow systems on multiple abstraction levels

A Performance Evaluation of DRAM Access for In-Memory Databases

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