Analyzing Consistency Issues in HMC Atomics

Kumar, Pranith; Nai, Lifeng; Kim, Hyesoon

doi:10.1145/2989081.2989104

Cited by 2 publications

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“…In fact, because identification of proper offloading candidates requires careful consideration of multiple factors such as cache performance, bandwidth consumption, and application behavior, this burden limits PIM applicability. In some cases, HMC-atomic instructions can violate memory consistency, but, as pointed out by others [26,28], graph-computing applications can safely use HMC-atomic instructions. This is because these applications perform read and atomic instructions at separate execution phases, which naturally prevents consistency violation.…”

Section: Burden On Programmersmentioning

confidence: 98%

“…Furthermore, the accessed data could be in the shared state in other processors, so another source of overhead is due to cache invalidation and coherence traffic. Because HMC-atomic instructions exploit MLP and the programming model of target applications does not require strict sequential consistency (SC) 3 , the execution of atomic operation will have less overhead than their execution on a host [26,28,29]. Fig.…”

Section: Preventing the Overhead Of Host Atomic Instructionsmentioning

confidence: 99%

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Cairo

Hadidi

Nai

Kim

2017

ACM Trans. Archit. Code Optim.

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Three-dimensional (3D)-stacking technology and the memory-wall problem have popularized processingin-memory (PIM) concepts again, which offers the benefits of bandwidth and energy savings by offloading computations to functional units inside the memory. Several memory vendors have also started to integrate computation logics into the memory, such as Hybrid Memory Cube (HMC), the latest version of which supports up to 18 in-memory atomic instructions. Although industry prototypes have motivated studies for investigating efficient methods and architectures for PIM, researchers have not proposed a systematic way for identifying the benefits of instruction-level PIM offloading. As a result, compiler support for recognizing offloading candidates and utilizing instruction-level PIM offloading is unavailable. In this article, we analyze the advantages of instruction-level PIM offloading in the context of HMC-atomic instructions for graphcomputing applications and propose CAIRO, a compiler-assisted technique and decision model for enabling instruction-level offloading of PIM without any burden on programmers. To develop CAIRO, we analyzed how instruction offloading enables performance gain in both CPU and GPU workloads. Our studies show that performance gain from bandwidth savings, the ratio of number of cache misses to total cache accesses, and the overhead of host atomic instructions are the key factors in selecting an offloading candidate. Based on our analytical models, we characterize the properties of beneficial and nonbeneficial candidates for offloading. We evaluate CAIRO with 27 multithreaded CPU and 36 GPU benchmarks. In our evaluation, CAIRO not only doubles the speedup for a set of PIM-beneficial workloads by exploiting HMC-atomic instructions but also prevents slowdown caused by incorrect offloading decisions for other workloads. CCS Concepts: • Hardware → 3D integrated circuits; Emerging architectures; Memory and dense storage; • Software and its engineering → Compilers;

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Section: Burden On Programmersmentioning

confidence: 98%

Section: Preventing the Overhead Of Host Atomic Instructionsmentioning

confidence: 99%