Analytics and Metrology of Strained Silicon Structures by Raman and Nano-Raman Spectroscopy

Hecker, M.; Zhu, Liang; Georgi, Carsten; Zienert, I.; Rinderknecht, J.; Geisler, H.; Zschech, Ehrenfried

doi:10.1063/1.2799413

Cited by 23 publications

(14 citation statements)

References 1 publication

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“…Among several techniques for stress characterization, microRaman spectroscopy appears particularly useful and was recently applied to measure the near-surface local stress distribution in Si around Cu TSVs [11], [12]. All of the previous Raman measurements have been done, however, at room temperature (RT).…”

Section: Study Of Near-surface Stresses In Silicon Around Through-silmentioning

confidence: 99%

Study of Near-Surface Stresses in Silicon Around Through-Silicon Vias at Elevated Temperatures by Raman Spectroscopy and Simulations

Zhu

Zhang²,

et al. 2015

IEEE Trans. Device Mater. Relib.

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The near-surface stress distribution around Cu through-silicon vias (TSVs) was studied by micro-Raman spectroscopy along with finite-element analysis from room temperature to 100 • C. Temperature-dependent measurements, along with simulations, revealed that the stresses near TSVs can have two components: 1) the preexisting stress before copper filling; and 2) the coefficients of thermal expansion (CTE)-mismatch-induced stress. The CTE-mismatch-induced stress resulted in a mobility change, and a keep-out zone (KOZ) at elevated temperatures was also estimated, where the KOZ was defined as the region with a mobility change larger than or equal to 10%. Higher temperatures were shown to reduce the CTE-mismatch-induced stress component and resulted in the shrinkage of KOZs in Si. The preexisting stress was shown to be significant in a region equal to or larger than the KOZs induced by the CTE-mismatch-induced stress only and should be characterized and considered in the KOZ determination and the circuit design. Index Terms-3-D integrated circuit (IC), keep-out zone (KOZ), mobility, stress, through silicon via (TSV).

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Section: Study Of Near-surface Stresses In Silicon Around Through-silmentioning

confidence: 99%

Study of Near-Surface Stresses in Silicon Around Through-Silicon Vias at Elevated Temperatures by Raman Spectroscopy and Simulations

Zhu

Zhang²,

et al. 2015

IEEE Trans. Device Mater. Relib.

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“…Among several potential techniques, the microRaman spectroscopy appears particularly promising and was recently applied to measure the local stress distribution in Si near Cu TSVs. [13][14][15] This method is a spectroscopic technique where the stress magnitude is deduced from the frequency shift of the impinging laser light as a result of inelastic scattering by Si lattice. [16][17][18] The lateral resolution of microRaman spectroscopy is in the order of 0.5 lm, depending on the laser wavelength and the substrate lattice.…”

Section: Introductionmentioning

confidence: 99%

Micro-Raman spectroscopy and analysis of near-surface stresses in silicon around through-silicon vias for three-dimensional interconnects

Ryu

Zhao

Hecker

et al. 2012

Journal of Applied Physics

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102

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Three-dimensional integration with through-silicon vias (TSVs) has emerged as an effective solution to overcome the wiring limit imposed on device density and performance. However, thermal stresses induced in TSV structures raise serious thermomechanical reliability concerns. In this paper, we analyze the near-surface stress distribution in a TSV structure based on a semi-analytic approach and finite element method, in comparison with micro-Raman measurements. In particular, the depth dependence of the stress distribution and the effect of elastic anisotropy of Si are illustrated to properly interpret the Raman data. The effects of the surface oxide layer and metal plasticity of the via material on the stress and Raman measurements are discussed. The near-surface stress characteristics revealed by the modeling and Raman measurements are important for design of TSV structures and device integration.

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“…Under the [0 0 1] backscattering configuration, only the longitudinal Raman mode can be detected. Assuming a biaxial stress state near the wafer surface, the following relation can be deduced from the secular equation for (0 0 1) Si[19],…”

mentioning

confidence: 99%

Measurement and analysis of thermal stresses in 3D integrated structures containing through-silicon-vias

Jiang

Ryu

Zhao

et al. 2013

Microelectronics Reliability

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Analytics and Metrology of Strained Silicon Structures by Raman and Nano-Raman Spectroscopy

Cited by 23 publications

References 1 publication

Study of Near-Surface Stresses in Silicon Around Through-Silicon Vias at Elevated Temperatures by Raman Spectroscopy and Simulations

Study of Near-Surface Stresses in Silicon Around Through-Silicon Vias at Elevated Temperatures by Raman Spectroscopy and Simulations

Micro-Raman spectroscopy and analysis of near-surface stresses in silicon around through-silicon vias for three-dimensional interconnects

Measurement and analysis of thermal stresses in 3D integrated structures containing through-silicon-vias

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