Analytical Models for Drain Current and Gate Capacitance in Amorphous InGaZnO Thin-Film Transistors With Effective Carrier Density

Bae, Myunghan; Kim, Yong-Sik; Kong, Dongsik; Jeong, Hyun Kwang; Kim, Woojoon; Kim, Jaehyeong; Hur, Inseok; Kim, Dong Myong; Kim, Dae Hwan

doi:10.1109/led.2011.2164229

Cited by 43 publications

(18 citation statements)

References 5 publications

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“…In the amorphous TFTs, the field effect mobility is dominated by the amount of free carriers (Q f ree ) in the channel which is strongly dependent on the gate voltage (V gs ) and threshold voltage [9], [10]:…”

Section: B Pre-breakdown Degradation Due To Tlp Stressmentioning

confidence: 99%

Instability of Indium Zinc Oxide Thin-Film Transistors Under Transmission Line Pulsed Stress

Liu

Lei

et al. 2014

IEEE Electron Device Lett.

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The instability of indium zinc oxide thin film transistors (IZO TFTs) is investigated under transmission line pulsed (TLP) stress by applying repeated voltage pulses with different durations (50-200 ns) to the gate with grounded source and drain. Threshold voltage increases and then electron field effect mobility decreases after TLP stress. These results are due to electron trapping in the existing traps of gate oxide near the SiO 2 /IZO interface, which is verified by the subsequent annealing experiment. The instability behavior is also investigated by lowfrequency noise measurements before and after TLP stress. Furthermore, influences of stress voltage and pulsewidth on the degradation effect of IZO TFT are discussed. Index Terms-Indium zinc oxide (IZO), thin film transistor (TFT), transmission line pulse (TLP), electrostatic discharge (ESD), low frequency noise (LFN).

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Section: B Pre-breakdown Degradation Due To Tlp Stressmentioning

confidence: 99%

Instability of Indium Zinc Oxide Thin-Film Transistors Under Transmission Line Pulsed Stress

Liu

Lei

et al. 2014

IEEE Electron Device Lett.

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“…Here, we found that two factors, i.e., the Schottky-contact and the Poole-Frenkel mobility, needed to be taken into account in addition to the conventional mobility edge model. Thus we improved the DOS-based analytical I-V and C-V models [6] by employing a Schottky diode, the depletion capacitance, and the Poole-Frenkel mobility, as summarized in Table 1. In detail, the S/D contacts were modeled as back-to-back connected Schottky diodes.…”

Section: Analytical I-v and C-v Modelsmentioning

confidence: 99%

“…8(b)], which means that the detailed non-linearity of PTFTs is successfully reproduced with the improved analytical model. The analytical C-V model was also improved from [6] by adding the depletion capacitance (C dep ) for the depletion region of the active layer. It is consistent with the back-to-back Schottky contact model (Fig.…”

Section: Analytical I-v and C-v Modelsmentioning

confidence: 99%

Inkjet printed polymer SRAM-cell design for flexible FPGA with physical parameter-based TFT model

Jang

Lee

Kim

et al. 2013

2013 IEEE International Electron Devices Meeting

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AbstractsFor the feasibility of material-device-circuit co-design for polymer thin-film transistors, we established the density-of-states-based analytical model and the modelincorporated circuit simulator and performed the design of inkjet-printed polymer SRAM-cell for flexible FPGA. The sampling speed of 12~34 ms and the hold time of longer than 1 s were demonstrated. The model was verified by the low error (within 3%).1. Introduction Solution-processable polymer-based thin-film transistors (PTFTs) are suitable for flexible large-area electronics and have great potential as supplements to solid and expensive counterpart devices. For this reason, PTFTs have been applied to various applications such as displays, RFIDs, sensors, and actuators [1]. Furthermore, the 8-bit organic microprocessor has been demonstrated on plastic foil with emphasis on a low power consumption, which has opened the way to integrating small plastic circuits into everyday objects [2]. On the other hand, the PTFT-based user customizable logic paper has been adopted for the architecture of transmission-gates and ink-jet printed interconnects [3]. As the possibility of implementing innovative circuits with a reliable and PTFT technology increases, a systematic approach for material-device-circuit co-design becomes indispensable to the design methodology of PTFT-based circuits and systems in order to project and assess the promise of available applications and their performance, even in the early stage of developing this promising PTFT technology.In this work, we demonstrated a simple example of the material-device-circuit co-design, which was performed based on the extraction of the sub-bandgap density-of-states (DOS). We established DOS-based analytical I-V and C-V models, incorporating the model into a SPICE-based circuit simulator, finally, into the design of the PTFT-based SRAM-cell. The model-incorporated circuit simulator was verified by comparing the measured PTFT-based inverter characteristics with simulated results. In addition, it was found that our SRAM-cells which were optimized in perspective of the static noise margin (SNM) and the size of transistors showed the "write" speed of 12~34 ms and a "hold" time of longer than 1 sec. Notably, our approach is the first step for the material-device-circuit co-design of PTFT-based electronics because the SRAM-based "sample and hold" operation is either a critical function or a fundamental building block in the implemention of a basic logic circuit and/or flexible field-programmable gate array (FPGA). ExperimentalA polymer semiconductor (Poly (tetryldodecyloctathiophene-alt-didodecylbithiazole-co-tetryldodecylhexathiophene-alt -didodecylbithiazole); P(8T2Z-co-6T2Z)-12) [4] was dissolved in tetrahydronaphthalene (THN) at a concentration of 0.2 wt%, and then inkjet-printed via Dimatix printer. The solution-processed PTFT with a bottom-gate and bottom-source/drain (S/D) structure and its fabrication process were schematically illustrated in Fig. 1. Fig. 2 shows an optical image of the inkjet-p...

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“…For the circuit simulation, an analytical I-V and C-V model were established by modifying our previous n-type metal oxide TFT model [9] into the p-type counterpart. The equations of I-V and C-V model were basically similar to [9], and the parameterextracting procedure was illustrated in Fig. 2.…”

Section: Analytical Model and Its Incorporation Into Circuit Simulationmentioning

confidence: 99%

P.19: Density‐of‐States Based Device‐Circuit Co‐Design Platform for Solution‐Processed Organic Integrated Circuits

Jang

Kim

Lee

et al. 2013

Symp Digest of Tech Papers

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In this work, we propose the subgap density‐of‐states (DOS) based device‐circuit co‐design platform for solution‐processed organic integrated circuits. For the circuit simulation, analytical I‐V and C‐V model were established from experimentally extracted DOS parameters, incorporated into HSPICE via Verilog‐A, and verified by comparing the simulation result with the measured characteristics of inverter integrated with solution‐processed polymer‐based organic thin‐film‐transistors. Furthermore, as the case study, it was shown by using our well‐calibrated simulation platform that the pass‐transistor type logic was potentially promising in low‐power and high‐speed solution processed organic integrated circuits.

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Analytical Models for Drain Current and Gate Capacitance in Amorphous InGaZnO Thin-Film Transistors With Effective Carrier Density

Cited by 43 publications

References 5 publications

Instability of Indium Zinc Oxide Thin-Film Transistors Under Transmission Line Pulsed Stress

Instability of Indium Zinc Oxide Thin-Film Transistors Under Transmission Line Pulsed Stress

Inkjet printed polymer SRAM-cell design for flexible FPGA with physical parameter-based TFT model

P.19: Density‐of‐States Based Device‐Circuit Co‐Design Platform for Solution‐Processed Organic Integrated Circuits

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