Analytical Modeling of Dual Material Gate All around Stack Architecture of Tunnel FET

Balamurugan, N. B.; Priya, G. Lakshmi; Manikandan, S.; Srimathi, G.

doi:10.1109/vlsid.2016.74

Cited by 11 publications

(4 citation statements)

References 10 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…It is based on Moore’s law, which stipulates that every two years the count of transistors on a particular region of silicon becomes twice. FinFET’s appeal stems from its lower leakage current, higher performance, and a variety of implementation techniques including the usage of Tunnel FETs and Junctionless Tunnel FETs were also used in the literature for the SRAM design [ 8 , 9 , 10 , 11 ]. Scaling down, according to Moore’s law, provides a high integration density on the chip and aids in the management of the short channel effect.…”

Section: Implementation Of 6t-sram Using Cmos Finfet and Memristormentioning

confidence: 99%

See 1 more Smart Citation

Hybrid Silicon Substrate FinFET-Metal Insulator Metal (MIM) Memristor Based Sense Amplifier Design for the Non-Volatile SRAM Cell

et al. 2023

Self Cite

View full text Add to dashboard Cite

Maintaining power consumption has become a critical hurdle in the manufacturing process as CMOS technologies continue to be downscaled. The longevity of portable gadgets is reduced as power usage increases. As a result, less-cost, high-density, less-power, and better-performance memory devices are in great demand in the electronics industry for a wide range of applications, including Internet of Things (IoT) and electronic devices like laptops and smartphones. All of the specifications for designing a non-volatile memory will benefit from the use of memristors. In addition to being non-volatile, memristive devices are also characterized by the high switching frequency, low wattage requirement, and compact size. Traditional transistors can be replaced by silicon substrate-based FinFETs, which are substantially more efficient in terms of area and power, to improve the design. As a result, the design of non-volatile SRAM cell in conjunction with silicon substrate-based FinFET and Metal Insulator Metal (MIM) based Memristor is proposed and compared to traditional SRAMs. The power consumption of the proposed hybrid design has outperformed the standard Silicon substrate FinFET design by 91.8% better. It has also been reported that the delay for the suggested design is actually quite a bit shorter, coming in at approximately 1.989 ps. The proposed architecture has been made significantly more practical for use as a low-power and high-speed memory system because of the incorporation of high-K insulation at the interface of metal regions. In addition, Monte Carlo (MC) simulations have been run for the reported 6T-SRAM designs in order to have a better understanding of the device stability.

show abstract

Section: Implementation Of 6t-sram Using Cmos Finfet and Memristormentioning

confidence: 99%

“…The value of ‘q’ is calculated with the use of a sensory amplifier. To save the new value in the SRAM cell, the device must be set to “write mode” [ 8 , 9 ]. Changes to the SRAM cell are stored in advance when ‘q’ is set to zero or one.…”

Section: Implementation Of 6t-sram Using Cmos Finfet and Memristormentioning

confidence: 99%

Hybrid Silicon Substrate FinFET-Metal Insulator Metal (MIM) Memristor Based Sense Amplifier Design for the Non-Volatile SRAM Cell

et al. 2023

Self Cite

View full text Add to dashboard Cite

show abstract

“…Tunnel field-effect transistors (TFETs) are one of the next-generation candidates to compete with CMOS transistors at low voltage operation as it is able to achieve a subthreshold swing of less than 60 mV/decade [27]. Since the first introduction of TFET model [28], several research communities have provided open-source TFET models [16], [17], supporting different types of TFET physical structure, such as single-gate (SG) [19], [29], [30], double-gate (DG) [31]- [33], and gate-all-around [20], [34].…”

Section: Open-source Tfet's Modelsmentioning

confidence: 99%

FreePDK15TFET: An Open-Source Process Design Kit for 15nm CMOS and TFET devices

Chen

Zhang

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

View full text Add to dashboard Cite

With Moore's law reaching its limits, the use of new materials or new devices' structure has emerged as the next generation of CMOS devices. Among all, tunneling field-effect transistors (TFETs) have achieved a steep sub-threshold slope of less than 60mV/decade yet there is a lack of a complete process design kit (PDK) for large-scale circuit design. Hence, we present an open-source 15nm TFET PDK (15nmTFETPDK), which is based on FreePDK15 with additional support for open-source TFET models and its associated Cadence Virtuoso pcell in OA format and Mentor Calibre physical verification files. Our users can design their circuit in the Cadence Virtuoso platform and verify the consistency of the drawn layout and the circuit through the Calibre Platform. We hope that this open-source PDK allows them to further advance their research with new emerging devices.

show abstract

“…TFETs, due to their band‐to‐band (BTB) tunnelling mechanism, have emerged as one of the potential candidates in the field of low‐power applications. Various geometries of TFET have been postulated in literatures such as silicon (Si)‐on‐insulator (SOI) TFET [1, 2], double‐gate TFET [3], heterojunction TFET [4], dual‐material gate TFET [5] and circular‐gate TFET [6]. SOI devices produce several benefits such as reduced leakage current, minimised short channel effects, small drain body capacitance leading to better switching speed and excellent lateral and vertical isolations.…”

Section: Introductionmentioning

confidence: 99%

Analysis of kink reduction and reliability issues in low‐voltage DTD‐based SOI TFET

Ghosh

Bhowmick

2020

Micro & Nano Letters

View full text Add to dashboard Cite

This work proposes a silicon-on-insulator (SOI) tunnel field-effect transistor (TFET) with highly doped p ++-type L-shaped trench, which creates two dual tunnel diodes (DTDs) and compares the results with conventional SOI (C-SOI) TFET structure. Kink effect is analysed in SOI TFET, and for eliminating kink effect, a method has been proposed. The tunnel current of the DTD eliminates the accumulation of holes and mitigates the kink effect. The impact of temperature variation on kink effect has been studied. In the case of C-SOI device, kink effect postpones with the rise in temperature and the DTD-SOI device provides improved performance even at high temperature with no kink in the current-voltage characteristics. Moreover, the reliability issues of DTD-SOI device have been examined by considering various noise components in the presence of interface traps.

show abstract

Analytical Modeling of Dual Material Gate All around Stack Architecture of Tunnel FET

Cited by 11 publications

References 10 publications

Hybrid Silicon Substrate FinFET-Metal Insulator Metal (MIM) Memristor Based Sense Amplifier Design for the Non-Volatile SRAM Cell

Hybrid Silicon Substrate FinFET-Metal Insulator Metal (MIM) Memristor Based Sense Amplifier Design for the Non-Volatile SRAM Cell

FreePDK15TFET: An Open-Source Process Design Kit for 15nm CMOS and TFET devices

Analysis of kink reduction and reliability issues in low‐voltage DTD‐based SOI TFET

Contact Info

Product

Resources

About