Analytical modeling and evaluation of network-on-chip architectures

Suboh, Suboh; Bakhouya, Mohamed; Gaber, Jaafar; El‐Ghazawi, Tarek

doi:10.1109/hpcs.2010.5547064

Cited by 14 publications

(13 citation statements)

References 21 publications

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“…Packet loss rate is negligible compared to others signifying lower channel contention problem. A comparison on required additional area has been calculated followed by a method proposed by Suboh et al in [6]. A 31% to 13% area overhead has been ob- served by varying N from 1 to 4 for proposed topology over 2D mesh of size 8 × 8.…”

Section: Simulation Results and Discussionmentioning

confidence: 99%

A performance enhancing hybrid locally mesh globally star NoC topology

Das

Ghosal

Mohanty

et al. 2014

Proceedings of the 24th Edition of the Great Lakes Symposium on VLSI

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With the rapid increase in the chip density, Network-on-Chip (NoC) is becoming the prevalent architecture for today's complex chip multi processor (CMP) based systems. One of the major challenges of the NoC is to design an enhanced parallel communication centric scalable architecture for the on chip communication. In this paper, a hybrid Mesh based Star topology has been proposed to provide low latency, high throughput and more evenly distributed traffic throughout the network. Simulation results show that a maximum of 62% latency benefit (for size 8 × 8), 55% (for size 8 × 8), and 42% (for size 12 × 12) throughput benefits can be achieved for proposed topology over mesh with a small area overhead.

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Section: Simulation Results and Discussionmentioning

confidence: 99%

A performance enhancing hybrid locally mesh globally star NoC topology

Das

Ghosal

Mohanty

et al. 2014

Proceedings of the 24th Edition of the Great Lakes Symposium on VLSI

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“…In a different approach, authors of [7] introduced a low complexity analytic approach for the mean analysis of some performance metrics of NoCs. In 2010, Suboh et al proposed a Network Calculusbased methodology to evaluate the latency, throughput and cost metrics of a NoC-based architecture [8]. In 2012, Fischer and Fettweis presented accurate service estimation model for Round Robin arbiters used in Input-Queued NoC fabrics.…”

Section: Related Workmentioning

confidence: 99%

Providing performance guarantees in data center network switching fabrics

Hassen

Mhamdi

2016

2016 IEEE 17th International Conference on High Performance Switching and Routing (HPSR)

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Abstract-This paper proposes a novel and highly scalable multistage packet-switch design based on Networks-on-Chip (NoC). In particular, we describe a three-stage Clos packet-switch fabric with a Round-Robin packets dispatching scheme where each central stage module is an Output-Queued Unidirectional NoC (OQ-UDN), instead of the conventional single-hop crossbar. We test the switch performance under different traffic profiles. In addition to experimental results, we present an analytical approximation for the theoretical throughput of the switch under Bernoulli i.i.d arrivals. We also provide an upper-bound estimation of the end-to-end blocking probability in the proposed switch to help predict performance and to optimize the design.

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“…The NoC architecture can be viewed as a distributed system composed of autonomous nodes that communicate by exchanging messages through an on-chip interconnect 30 . The on-chip interconnect can be described as a graph OCI(V, E) whose nodes v ∈ V represent switches or cores and whose edges ∈ E represent the communication links between two neighboring nodes u and v. For each node v ∈ V , r v is the injection rate and for each link ∈ E, R denotes the guaranteed service rate or the link bandwidth.…”

Section: Network Calculus-based Modelmentioning

confidence: 99%

Performance evaluation and design tradeoffs of on-chip interconnect architectures

Bakhouya

Suboh

Gaber

et al. 2011

Simulation Modelling Practice and Theory

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Network-on-Chip (NoC) has been proposed as an alternative to bus-based schemes to achieve high performance and scalability in System-on-Chip (SoC) design. Performance analysis and evaluation of on-chip interconnect architectures are widely based on simulations, which become computationally expensive, especially for large-scale NoCs. In this paper, a Network Calculusbased methodology is presented to analyze and evaluate the performance and cost metrics, such as latency and energy consumption. The 2D Mesh, Spidergong, and WK-recursive on-chip interconnect architectures are analyzed using this methodology and results are compared with those produced using simulations. The values obtained by simulations and by analysis show similar trends in the same order of magnitude. Furthermore, WK outperforms the other on-chip interconnects in all considered metrics.

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Analytical modeling and evaluation of network-on-chip architectures

Cited by 14 publications

References 21 publications

A performance enhancing hybrid locally mesh globally star NoC topology

A performance enhancing hybrid locally mesh globally star NoC topology

Providing performance guarantees in data center network switching fabrics

Performance evaluation and design tradeoffs of on-chip interconnect architectures

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