Analytical model including the fringing-induced barrier lowering effect for a dual-material surrounding-gate MOSFET with a high-κ gate dielectric

Abstract

By solving Poisson's equation in both semiconductor and gate insulator regions in the cylindrical coordinates, an analytical model for a dual-material surrounding-gate (DMSG) metal-oxide semiconductor field-effect transistor (MOSFET) with a high-κ gate dielectric has been developed. Using the derived model, the influences of fringing-induced barrier lowering (FIBL) on surface potential, subthreshold current, DIBL, and subthreshold swing are investigated. It is found that for the same equivalent oxide thickness, the gate insulator with high-κ dielectric degrades the short-channel performance of the DMSG MOSFET. The accuracy of the analytical model is verified by the good agreement of its results with that obtained from the ISE three-dimensional numerical device simulator.

Quasi-two-dimensional threshold voltage model for junctionless cylindrical surrounding gate metal-oxide-semiconductor field-effect transistor with dual-material gate

“…This step potential ensures better screening of the channel region near the source from drain voltage of JLDMCSG. [3] In addition, good agreement between the results of our model and those of ISE is obtained. Figure 3 shows the central potential profile for JLSMCSG and JLDMCSG with different drain voltages.…”

“…Due to superior gate controllability, the cylindrical surrounding-gate (CSG) metal-oxide-semiconductor fieldeffect transistor (MOSFET) has been regarded as one of the most promising devices to extend the scaling limit of CMOS technology. [1][2][3] However, the formation of the abrupt source and drain junctions in the conventional CSG MOSFET imposes several challenges on doping techniques and thermal budget. [4] In order to alleviate these problems, the junctionless (JL) MOSFET has been proposed recently.…”

Interfacial characteristics of Al/Al2O3/ZnO/n-GaAs MOS capacitor

“…Based on the experimental C-V curves, we can extract the values of C s using Eq. (1). Then the relationship between ψ s and V g can be extracted from Eq.…”

“…However, a major problem is the lack of high quality and thermodynamically stable dielectric that can be used to fabricate high quality GaAs MOSFET. [1] High interface trap density [2] can lower the channel electron mobility, thus leading to the degradation of device electrical properties. For GaAs MOS devices, the values of interface trap density reported by different authors were between 5×10 11 cm −2 •eV −1 -6.9×10 12 cm −2 •eV −1 , [3] but for Si/SiO 2 MOS, it is 10 10 cm −2 •eV −1 .…”

A two-dimensional analytical subthreshold behavior model for junctionless dual-material cylindrical surrounding-gate MOSFETs

“…Due to the ideal symmetry structure and excellent gate control ability, cylindrical surrounding-gate (CSG) metaloxide-semiconductor field-effect transistors (MOSFETs) are regarded as the most promising devices for extending the scaling limit of CMOS technology. [1][2][3][4] However, the formation of the ultra-sharp source/drain junction of CSG MOS-FETs still imposes several challenges on the doping techniques and thermal budget. [5,6] In order to overcome these challenges, junctionless cylindrical surrounding-gate (JLCSG) MOSFETs have been proposed, [7] and their superior characteristics have been demonstrated by experiments and analytical models.…”