Analytical Loss Model of High Voltage GaN HEMT in Cascode Configuration

Huang, Xiucheng; Li, Qiang; Liu, Zhengyang; Lee, Fred C.

doi:10.1109/tpel.2013.2267804

Cited by 220 publications

(48 citation statements)

References 21 publications

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“…For the double-pulse test, the load current can be considered constant for the duration of a switching cycle. Hence, the load inductance can be equivalent to a constant current source I L with its parasitic resistance being excluded in this paper [13,21]. In Figure 2, L Y X (X = F or R; Y = L, D, G, S, C or m) means parasitic inductors.…”

Section: Analysis and Suppression Of Utomentioning

confidence: 99%

Analysis and Suppression of Unwanted Turn-On and Parasitic Oscillation in SiC JFET-Based Bi-Directional Switches

Wang

Yang

et al. 2018

Electronics

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Silicon Carbide (SiC)-based Bi-Directional Switches (BDS) have great potential in the construction of several power electronic circuits including multi-level converters, solid-state breakers, matrix converters, HERIC (high efficient and reliable inverter concept) photovoltaic grid-connected inverters and so on. In this paper, two issues with the application of SiC-based BDSs, namely, unwanted turn-on and parasitic oscillation, are deeply investigated. To eliminate unwanted turn-on, it is proposed to add a capacitor (C X ) paralleled at the signal input port of the driver IC (integrated circuit) and the capacitance range of C X is also analytically derived to guide the selection of C X . To mitigate parasitic oscillation, a combinational method, which combines a snubber capacitor (C J ) paralleled with the JFET (Junction Field Effect Transistor) and a ferrite ring connected in series with the power line, is proposed. It is verified that the use of C J mainly improves the turn-off transient and the use of a ferrite ring damps the current oscillation during the turn-on transient significantly. The effects of the proposed methods have been demonstrated by theoretical analysis and verified by experimental results.

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Section: Analysis and Suppression Of Utomentioning

confidence: 99%

Analysis and Suppression of Unwanted Turn-On and Parasitic Oscillation in SiC JFET-Based Bi-Directional Switches

Wang

Yang

et al. 2018

Electronics

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show abstract

“…Industrial power drive circuits are usually in a normally-off configuration to enable fail-safe operation and a simple gate drive. To apply a normally-on GaN HEMT in circuit design, a low-voltage MOSFET is used in series to drive the GaN HEMT, which is a popular approach and well-known as cascode structure (Curatola et al, 2014;Li et al, 2016;Xiucheng, Qiang, Zhengyang, & Lee, 2014). Figure 5 shows the cascode GaN FET device circuit hermetically sealed in the four-pin metal case TO-257 package (H.-P. Chou, Cheng, Cheng, & Chuang, 2016).…”

Section: Cascode Gan-hemts Packagingmentioning

confidence: 99%

Thermal performance evaluation of cascode Paralleled-GaN-HEMTs packaging for high power switching applications

Chou

Cheng

2017

JTST

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“…The phenomenon of dynamic current sharing imbalance during turn-on and turn-off transients are quite different due to the unique cascode structure current source turn-off mechanism [13]. This will cause the oscillation of the turn-off transient to be much shorter in time but larger in amplitude.…”

Section: A Critical Static Parametersmentioning

confidence: 99%

Evaluation of high voltage cascode GaN HEMTs in parallel operation

Zhang

Wen

et al. 2016

2016 IEEE Applied Power Electronics Conference and Exposition (APEC)

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Paralleling devices is an effective way to achieve higher power applications while still having the convenience brought by discrete devices. However, very few papers investigate the challenges of paralleling Gallium Nitride high electron mobility transistors (GaN HEMTs) in cascode configuration, especially the potential failure modes and its related mechanisms. In this paper, a comprehensive study on paralleled high voltage cascode GaN HEMTs is presented. The influence of paralleling cascode GaN HEMTs on the circuit's stray inductance is studied. Potential operation failure modes and the mechanisms of the cascode GaN HEMTs parallel operation were analyzed in detail. The Ansoft Q3D FEA tool and SPICE-based simulation model were used together to quantify the impacts of the circuit and device mismatch on the paralleled GaN HEMTs operation. The SPICE model is validated by the experimental results

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Analytical Loss Model of High Voltage GaN HEMT in Cascode Configuration

Cited by 220 publications

References 21 publications

Analysis and Suppression of Unwanted Turn-On and Parasitic Oscillation in SiC JFET-Based Bi-Directional Switches

Analysis and Suppression of Unwanted Turn-On and Parasitic Oscillation in SiC JFET-Based Bi-Directional Switches

Thermal performance evaluation of cascode Paralleled-GaN-HEMTs packaging for high power switching applications

Evaluation of high voltage cascode GaN HEMTs in parallel operation

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