Analytical jitter estimation of two-stage output buffers with supply voltage fluctuations

Park, Eunkyeong; Kim, Jingook; Kim, Hyungsoo; Shon, Kwansu

doi:10.1109/isemc.2014.6898945

Cited by 19 publications

(4 citation statements)

References 6 publications

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“…The timing analysis at the output of a delay-line or a tapered buffer in the presence of PSN can be performed using various methods [4], [6], [9]- [11], [14], [15]. In this paper, a simplified semi-analytical approach is developed for the analysis of TIE (as well as the jitter) at the output of a delayline or tapered buffer that are designed using CMOS inverters.…”

Section: Problem Formulationmentioning

confidence: 99%

A Thomas Algorithm-Based Generic Approach for Modeling of Power Supply Induced Jitter in CMOS Buffers

et al. 2019

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This paper presents an efficient and generic method for analysis of power supply induced jitter (PSIJ) in a chain of CMOS inverters as well as tapered buffers due to multiple deterministic noise sources. Generalised semi-analytical relations between noise and PSIJ are developed using Thomas algorithm. The proposed analysis can be used for both cases of same size of inverters as well as tapered buffers, and also for considering the effect of on-chip and off-chip interconnects. The validity and the efficiency of the proposed modeling is demonstrated for various applications of chain of inverters such as buffers in clock distribution, delay locked loops and I/Os, etc. INDEX TERMS CMOS inverter, chain of inverters, clock-network, delay-line, I/O, jitter, power supply noise, power supply induced jitter, time interval error, tapered buffer. APPENDIX C FORMULATION OF TRI-DIAGONAL MATRIX FOR EXAMPLE-3

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Section: Problem Formulationmentioning

confidence: 99%

A Thomas Algorithm-Based Generic Approach for Modeling of Power Supply Induced Jitter in CMOS Buffers

et al. 2019

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“…Moreover, distinct PDNs are commonly deployed for powering the pre-driver and last stage, V DD /V SS and V DDQ /V SSQ , respectively, as shown in the IO buffer circuit diagram of Figure 2. The device's switching currents in the last stage (e.g., i H (t) and i L (t)) and pre-driver stage (e.g., i H p (t) and i Lp (t)), flowing via the PDN, produce the PGSV variations, generating the timing distortions at the output voltage, which is defined by the P/G supply-induced jitter (PGSIJ) [7]. and the massive high-speed data processing requiring fast DDR memory, server CPU, and multi-level signaling with low-level power rail voltages for power saving [2,3].…”

Section: Introductionmentioning

confidence: 99%

“…Previous IO buffer-modelling methodologies, which can be classified either based on the equivalent circuit input-output buffer information specification (IBIS) or parametric curve fitting [8,9], have not clearly addressed the PVT corner simulation and its importance in the model's generation steps, worst corner identification, and in the validation of model performance. In fact, the standard multiport behavioral model structure that describes the electrical behaviors of the IO buffer circuit, while considering the PGSV variables [7][8][9], is: Since these supplies are not constant due to high-current switching through the predriver's PDN, therefore, the IBIS model fails to accurately predict the timing distortion originating from V DD , the voltage noise which affects the output eye jitter. Moreover, previous works presented an extended equivalent circuit behavioral model for SiPI simulation in the pre-driver and the driver's last stage [10][11][12].…”

Section: Introductionmentioning

confidence: 99%

Analysis of Pre-Driver and Last-Stage Power—Ground-Induced Jitter at Different PVT Corners

Souilem

Melício

Dghais

et al. 2022

Sensors

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This paper presents the study of power/ground (P/G) supply-induced jitter (PGSIJ) on a cascaded inverter output buffer. The PGSIJ analysis covers the IO buffer transient simulation under P/G supply voltage variation at three process, voltage, and temperature (PVT) corners defined at different working temperatures and distinct P/G DC supply voltages at the pre-driver (i.e., VDD/VSS) and last stage (i.e., VDDQ/VSSQ). Firstly, the induced jitter contributions by the pre-driver, as well as the last, stage are compared and studied. Secondly, the shared and decoupled P/G supply topologies are investigated. The outcomes of these simulation analyses with respect to worst case jitter corners are determined, while highlighting the importance of modeling the pre-driver circuit behavior to include the induced jitter in the input–output buffer information specification (IBIS)-like model. Accordingly, the measured PGSIJ depends on the corners to be analyzed and, therefore, the designer needs to explore the worst-case corner for the driver’s technology node and the most supply voltage noise affecting the jitter output for signal and power integrity (SiPI) simulations. Finally, the jitter transfer function sensitivity to the amplitude and frequency/phase variations of the separate and combined impacts of the pre-driver and last stage are explored, while discussing the superposition of the power supply induced jitter (PSIJ) induced by both the driver’s IO stages under small signal and large signal supply voltage variations. The linear superposition of the separate PSIJ effects by the pre-driver and last stage depends on the amplitude of the variation of the supply voltage that can drive the transistor to their nonlinear working regions.

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“…The key concept of power supply induced jitter sensitivity (PSIJS) has been proposed and applied to PSIJ analysis. PSIJS of single buffer [26] [27] and PSIJ of two-stage [28] and multi-stage [29] buffers have been studied. In this dissertation a simple and concise PSIJS expression of multi-stage buffer chain [30] is derived, which can be used to calculate PSIJ of buffer chains quickly and accurately.…”

Section: Ddr Controller and Design Challengesmentioning

confidence: 99%

Reduction of Power Supply Induced Jitter with Applications to DDR Controllers

Wang¹

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It is desirable to improve the tradeoff between the power supply induced jitter (PSIJ) performance and the cost for the clock distribution circuit in a double data rate (DDR) controller. This thesis proposes the following techniques to achieve the goal: The static phase offset (SPO) is the dominant mechanism causing reference spurs in the spectrum of the multiplying delay-locked loop (MDLL) output. With a high-gain stage inserted between the phase detector/phase frequency detector and the charge pump, the equivalent SPO has been decreased by a factor equal to the gain of the gain stage. The

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Analytical jitter estimation of two-stage output buffers with supply voltage fluctuations

Cited by 19 publications

References 6 publications

A Thomas Algorithm-Based Generic Approach for Modeling of Power Supply Induced Jitter in CMOS Buffers

A Thomas Algorithm-Based Generic Approach for Modeling of Power Supply Induced Jitter in CMOS Buffers

Analysis of Pre-Driver and Last-Stage Power—Ground-Induced Jitter at Different PVT Corners

Reduction of Power Supply Induced Jitter with Applications to DDR Controllers

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