Analytical dynamic power model for LUT based components

Najoua, Chalbi; Boubaker, Mohamed; Hedi, Bedoui Mohamed

doi:10.1109/dtis.2012.6232957

Cited by 7 publications

(7 citation statements)

References 10 publications

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“…Estimation of the power consumption for FPGAs is a topic which is discussed in [24], where precharacterizationbased macro-modeling is used to capture average switching power per access to both look-up tables (LUTs) and registers. Another linear-based model for the dynamic power is proposed in [25], in which the switching activity from the RTlevel is utilized to estimate component power breakdowns for the FIR filter application with a fair error (10% of average error). Power models for multiprocessor SoC (MPSoC) circuit on FPGA is conducted in [26].…”

Section: Neural Networkmentioning

confidence: 99%

A Design-Time Method for Building Cost-Effective Run-Time Power Monitoring

Najem

Benoit

Ahmad

et al. 2017

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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The emergence of power as a first-class design constraint has fueled the proposal of a growing number of optimization techniques, seeking the best tradeoff to reach the maximum energy efficiency. Effective adaptation strategies depend critically on the monitoring method as an incorrect assessment of the system's state will result in poor decision making. Yet it is indeed a fundamental issue: how to get a precise estimation of the system's state, and especially in a cost-effective way? We address this question for the self-observation of the power consumption. We develop a method that combines several data mining algorithms to monitor the toggling activity on a few relevant signals selected at the register transfer-level. Our approach is based on a generic flow that is able to produce a power model for any register transfer level (RTL) circuit on any technology. This contribution is evaluated on a system on chip RTL model implemented on an field-programmable gate array technology. The experiments demonstrate that the proposed method achieves the accuracy of analog power sensors (error lower than 1%) at a finer granularity and in a cost-effective way. Index Terms-Data mining, design-time method, fieldprogrammable gate array (FPGA), power modeling, register transfer-level, system on chip (SoC) monitoring.

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Section: Neural Networkmentioning

confidence: 99%

A Design-Time Method for Building Cost-Effective Run-Time Power Monitoring

Najem

Benoit

Ahmad

et al. 2017

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…The switch-level interconnect model is developed by fitting a switching power formula with capacitance values and the signal transition rate extracted at each node. In [18], the same idea was employed, but power lookup models were generalized for arithmetic operators (e.g., adders, LUT-based multipliers and digital signal processing (DSP)-based multipliers) with different operating frequencies, signal switching activities and data widths.…”

Section: Related Workmentioning

confidence: 99%

“…Low-level power models are also specialized in their targeted FPGA families and devices, making them difficult to migrate to other FPGA families. Moreover, low-level power models, such as those proposed in [17] and [18], usually require intensive computation to calculate power for every component independently. This issue adds to their inefficiency considering real-time detection.…”

Section: Related Workmentioning

confidence: 99%

An Ensemble Learning Approach forIn-SituMonitoring of FPGA Dynamic Power

Lin

Sinha

Zhang

2019

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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As field-programmable gate arrays become prevalent in critical application domains, their power consumption is of high concern. In this paper, we present and evaluate a power monitoring scheme capable of accurately estimating the runtime dynamic power of FPGAs in a fine-grained timescale, in order to support emerging power management techniques. In particular, we describe a novel and specialized ensemble model which can be decomposed into multiple customized decision-tree-based base learners. To aid in model synthesis, a generic computer-aided design flow is proposed to generate samples, select features, tune hyperparameters and train the ensemble estimator. Besides this, a hardware realization of the trained ensemble estimator is presented for on-chip real-time power estimation. In the experiments, we first show that a single decision tree model can achieve prediction error within 4.51% of a commercial gate-level power estimation tool, which is 2.41-6.07× lower than provided by the commonly used linear model. More importantly, we study the extra gains in inference accuracy using the proposed ensemble model. Experimental results reveal that the ensemble monitoring method can further improve the accuracy of power predictions to within a maximum error of 1.90%. Moreover, the lookup table (LUT) overhead of the ensemble monitoring hardware employing up to 64 base learners is within 1.22% of the target FPGA, indicating its lightweight and scalable characteristics.

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“…These models may be obtained by applying a linear regression on parameters of interest. This enables more flexibility, to the detriment of a loss of accuracy [12]. A tool called RTLEst [13] uses linear regression to automatically generate analytical power models.…”

Section: Related Workmentioning

confidence: 99%