Analytical Bounds for Optimal Tile Size Selection

Abstract

Abstract. In this paper, we introduce a novel approach to guide tile size selection by employing analytical models to limit empirical search within a subspace of the full search space. Two analytical models are used together: 1) an existing conservative model, based on the data footprint of a tile, which ignores intra-tile cache block replacement, and 2) an aggressive new model that assumes optimal cache block replacement within a tile. Experimental results on multiple platforms demonstrate the practical effectiveness of the approach by reducing the search space for the optimal tile size by 1,307× to 11,879× for an Intel Core-2-Quad system; 358× to 1,978× for an Intel Nehalem system; and 45× to 1,142× for an IBM Power7 system. The execution of rectangularly tiled code tuned by a search of the subspace identified by our model achieves speed-ups of up to 1.40× (Intel Core-2 Quad), 1.28× (Nehalem) and 1.19× (Power 7) relative to the best possible square tile sizes on these different processor architectures. We also demonstrate the integration of the analytical bounds with existing search optimization algorithms. Our approach not only reduces the total search time from Nelder-Mead Simplex and Parallel Rank Ordering methods by factors of up to 4.95× and 4.33×, respectively, but also finds better tile sizes that yield higher performance in tuned tiled code.

Inter-Tile Reuse Optimization Applied to Bandwidth Constrained Embedded Accelerators

“…The tile size selection problem is not solved, with analytical bounds and empirical search methods it is possible to find good performing tile parameters for CPU caches [9]. This work is extended with multi-level caches, conflict misses, and vectorization [10].…”

A multi-objective auto-tuning framework for parallel codes

“…tile sizes, loop ordering and unrolling factors) for individual code regions. However, while a carefully selected and tuned transformation sequence might be beneficial for one objective, the same may have adverse consequences on others [6]. Many successful practical auto-tuning solutions focus on specific applications [2], [3].…”

“…Many successful practical auto-tuning solutions focus on specific applications [2], [3]. For more generic, compiler-based approaches, however, the prohibitively large and complex optimization problem of selecting, customizing and ordering transformations to obtain an optimal variant of a user's input code is still among the most fundamental open issues in compiler research [6]- [10].…”

Hardware-Aware Tiling Optimization for Multi-Core Systems

“…During the compilation process, the compiler should decide how to tile the loops so that the number of cache misses is minimized. The problem of analytically finding the best partition of data in the general case for a multilevel system of cache memory is classified as NP hard [19]. It is not possible to determine in finite time how to place program data into the computer memory so that the time necessary for data transport is minimal.…”

“…One of the available techniques for improving memory performance is tiling [19]. The main aim of this optimization is to maximally reuse the fastest cache memory.…”