Analysis Techniques for SIMD Machine Interconnection Networks and the Effects of Processor Address Masks

Siegel, Howard Jay

doi:10.1109/tc.1977.5009294

Cited by 85 publications

(27 citation statements)

References 19 publications

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“…The nomenclature of this section is due to Siegel [11]. The Cube network is similar to the one implemented in Staran, the PM2I network is similar to Feng's Data Manipulator, while the WPM2I is Siegel's brainchild.…”

Section: Message Broadcasting On Cube Pm2i and Wpm2i Computersmentioning

confidence: 99%

“…The PM2I network has 2 log N = 2m settings, corresponding to the addition or subtraction mod N of 2' for 0 < i < m. The WPM2I connections are similar to those of the PM2I network, except any "carry" or "borrow" will "wrap around" to bit bi2. Lower b6unds for message broadcasting on these computers are implicit in the work of Siegel [11]. The PM2I (or WPM2I) takes at least log N (or (log N)/2) time to perform a "shuffle," which is a legal message broadcasting pattern.…”

Section: Message Broadcasting On Cube Pm2i and Wpm2i Computersmentioning

confidence: 99%

“…This data transfer is modeled as the routing of messages, each originating at a processing element and destined for some-subset of the other processing elements. There have been many papers treating particular message routing patterns on particular networks (Stone [12], Siegel [11], Orcutt [8], etc.). The algorithm based on the GCN of this paper performs near-optimally on any message broadcasting pattern in which each processing element receives one message on several popular SIMD interconnection networks.…”

Section: Introductionmentioning

confidence: 99%

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Generalized Connection Networks for Parallel Processor Intercommunication

Thompson

1978

IEEE Trans. Comput.

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Abstract-A generalized connection network (GCN) is a switching network with N inputs and N outputs that can be set to pass any of the NN mappings of inputs onto outputs. This paper demonstrates an intimate connection between the problems of GCN construction, message routing on SIMD computers, and "resource partitioning." A GCN due to Ofman [7] is here improved to use less than 7.6N log N contact pairs, making it the minimal known construction.Any GCN construction leads to a new algorithm for the broadcast of messages among processing elements of an SIMD computer when each processing element is to receive one message. Previous approaches to message broadcasting have not handled the problem in its full generality. The algorithm arising from this paper's GCN takes 8 log N (or 13N112) routing steps on an N element processor of the perfect shuffle (or mesh-type) variety.If each resource in a multiprocessing environment is assigned one output of a GCN, private buses may be provided for any number of disjoint subsets of the resources. The partitioning construction derived from this paper's GCN has 5.7N log N switches, providing an alternative to "banyan networks" with O(N log N) switches but incomplete functionality.

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Section: Message Broadcasting On Cube Pm2i and Wpm2i Computersmentioning

confidence: 99%

Section: Message Broadcasting On Cube Pm2i and Wpm2i Computersmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Generalized Connection Networks for Parallel Processor Intercommunication

Thompson

1978

IEEE Trans. Comput.

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“…Theoretically, every opération could be accompanied by a mask. There are various représentations of masks [17]. When an opération is accompanied by a mask, only PE's whose address (PEN) matches the mask will exécute that instruction.…”

Section: A Parallel Program For the Simplex Methodsmentioning

confidence: 99%

On the application of parallel architectures to a class of operations research problems

Dutta¹,

Siegel²,

Whinston³

1983

RAIRO-Oper. Res.

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“…In addition to the data manipulator, various interconnection networks have been investigated by many researchers, for example Stone [93], Lawrie [94], Lang [95], and Siegel [96,97]. Interested readers are referred to references [93][94][95][96][97]. …”

Section: Ss Yau and Hs Fungmentioning

confidence: 99%

Associative Processor Architecture—a Survey

Yau

Fung

1977

ACM Comput. Surv.

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A survey of the architecture of various associative processors is presented with emphasis on their characteristics, categorization, and implementation, and especially on recent developments. Based on their architecture, associative processors are classified into four categories, namely fully parallel, bit-serial, word-serial and block-oriented. The fully parallel associative processors are divided into two classes, word-orgamzed and distributed logic associative processors. Keywords and Phrases:Associative processors, computer architecture, categomzation, implementation, hardware, large-scale integration, fully parallel, bit-serial, word-serial, block-ormnted, distributed logic CR Categories: 3. 80, 6.22, 6.30, 6.31, 6.32, 6.33, 6.34 INTRODUCTIONAn associative processor can generally be described as a processor which has the following two properties: 1) Stored data items can be retrieved using their content or part of their content (instead of their addresses); and 2) data transformation operations, both arithmetic and logical, can be performed over many sets of arguments with a single instruction. Because of these parallel processing characteristics, associative processors have a much faster data processing rate than conventional sequential computers, and hence are more effective in handling many types of information processing problems such as information storage and retrieval of rapidly changing databases, fast search of a large database, arithmetic and logical operations on large sets of data, control and executive functions in large-scale computer systems, radar signal tracking and processing, and weather prediction computations. However, because of their relatively high implementation cost, associative processors are usually used in conjunction with standard sequential computer systems so that many required highspeed parallel processing tasks which cannot be effectively executed by sequential processors are performed by associative processors. Because of the rapid development of large-scale integrated-circuit (LSI) technology, the implementation cost of associative processors will be greatly reduced and it is anticipated that associative processors will be used more extensively for enhancing the performance of many special-purpose and general-purpose computer systems. Although there have been several papers providing either tutorials or literature surveys on associative processors [1-5], a number of new developments have not been described in any of the previous survey papers. In this paper, we will present a survey of the architecture of various associative processors, with emphasis on their characteristics, categorization, and implementation, and especially recent developments.

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Analysis Techniques for SIMD Machine Interconnection Networks and the Effects of Processor Address Masks

Cited by 85 publications

References 19 publications

Generalized Connection Networks for Parallel Processor Intercommunication

Generalized Connection Networks for Parallel Processor Intercommunication

On the application of parallel architectures to a class of operations research problems

Associative Processor Architecture—a Survey

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