Analysis of the Model Checkers' Input Languages for Modeling Traffic Light Systems

Abstract

Problem statement: Model checking is an automated verification technique that can be used for verifying properties of a system. A number of model checking systems have been developed over the last few years. However, there is no guideline that is available for selecting the most suitable model checker to be used to model a particular system. Approach: In this study, we compare the use of four model checkers: SMV, SPIN, UPPAAL and PRISM for modeling a distributed control system. In particular, we are looking at the capabilities of the input languages of these model checkers for modeling this type of system. Limitations and differences of their input language are compared and analyses by using a set of questions. Results: The result of the study shows that although the input languages of these model checkers have a lot of similarities, they also have a significant number of differences. The result of the study also shows that one model checker may be more suitable than others for verifying this type of systems Conclusion: User need to choose the right model checker for the problem to be verified.

Modeling Distributed Real-time Elevator System by Three Model Checkers

“…There are a lot of studies about comparison concerning model checker and which type of system more appropriate to be verified by which model checkers. Samat et al [12] compared are analyzed the input language of SMV, SPIN, UPPAAL and PRISM, and they described the limitations and differences of the input language of the four tools through modeling and verifying a traffic light system. And they got a conclusion that PROMELA, the input language of SPIN, is more appropriate for the description of traffic lights system.…”

Conditioned Slicing for Efficient Multiway Decision Graphs Model-Checker

“…The following definitions are derived from previous research in program slicing (Weiser, 1984;Samat et al, 2011;Tip, 1995). Interested researchers may check the given papers for detailed descriptions.…”

“…Nowadays, designers use Hardware Description Languages (HDLs) ) (Samat et al, 2011) to describe hardware designs at different levels, from high level of abstraction to low level circuits. One of the main advantages of using HDLs is that they can be formally verified to ensure the correctness of the designs at the different levels.…”