Analysis of the impact of prototyping‐related parasitic effects in a hybrid GaN power amplifier for 5G FR1 applications

Abstract

This article analyses the impact of parasitic effects encountered in the manufacturing of a Gallium Nitride power amplifier optimized for a specific trade‐off of efficiency and linearity at 5G FR1 frequencies. The analysis focuses on an example based on a packaged transistor and implemented in hybrid technology, adopting a two‐layer printed circuit board for passive distributed elements and surface‐mount lumped components. The design is summarized, and the focus is then posed on the comparison of simulated and measured results, the main causes of inaccuracy in their agreement, and a simple way of reproducing these in simulation. The mechanical stability of the assembly and the sensitivity of the second harmonic control are identified as the main sources of performance degradation. These effects are correctly modeled at the simulation level thanks to the insertion of specific parasitic lumped elements but could not be fully eliminated at the experimental level in this specific prototype. However, post‐tuning performed on the prototype, guided by the proposed analysis, still allows to reach satisfactory performance although somewhat sub‐optimal compared to the one expected from simulations. At 3.5 GHz, the re‐tuned PA demonstrates a measured output power in excess of 37.5 dBm at saturation, with associated gain higher than 14 dB and PAE of 60%. In a 2‐tone test with 20 MHz spacing, the IMD3 remains lower than −30 dBc up to 29 dBm of output power with a corresponding PAE of the order of 32%.

DC‐bias and temperature included CSWPL model for RF power transistors

“…Gallium nitride (GaN) high-electron-mobility transistors (HEMTs) have been widely used in PA design because of its large breakdown voltage, high operating frequency, and significant power density, 1,2 making this outstanding technology very well suited for high-power high-frequency applications. [3][4][5][6][7] During the past few decades, a series of high-efficiency PA architectures have been proposed. 1,2,8,9 In order to facilitate high-fidelity simulations of PA circuits for real-world performance, highly accurate transistor models are becoming more and more important.…”