Analysis of the back gate effect on the breakdown behaviour of SOI LDMOS transistors

Schwantes, S.; Florian, T.; Gräf, M.; Dietz, F.; Dudek, V.

doi:10.1109/essder.2004.1356537

Cited by 11 publications

(8 citation statements)

References 5 publications

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“…For 0-V gate voltage, the device is turned off. No current is conducted through the drift region and the back-gate bias dependence takes the bell shape, which has been discussed in detail in [1] and [3]. However, for gate voltages larger than the threshold voltage, the dependence changes significantly.…”

Section: Breakdown Measurementsmentioning

confidence: 95%

“…The body is pushed into deep depletion rather than into inversion. Device simulation reveals that at drain breakdown inversion at the buried oxide interface in the body requires at least a V BG of +80 V for this technology [1]. Even after the onset of an inversion layer, the electron current is preferably conducted at the surface due to the electric field caused by the front gate.…”

Section: Parasitic Bipolar Actionmentioning

confidence: 99%

“…We will refer to it as the back-gate in the following. Recently, it has been shown that the back-gate has a significant impact on the OFF-state (gate-to-source voltage equals 0 V) drain breakdown voltage of lateral SOI DMOS devices [1]- [3]. But, nothing has been reported about how the ON-state drain breakdown voltage (gate-to-source voltage larger than the threshold voltage) gets affected.…”

Section: Introductionmentioning

confidence: 98%

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Analysis of the Back-Gate Effect on the on-State Breakdown Voltage of Smartpower SOI Devices

Schwantes¹,

Furthaler²,

Schauwecker³

et al. 2006

IEEE Trans. Device Mater. Relib.

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This paper discusses the impact of the back-gate bias on the ON-state drain breakdown voltage of high-voltage silicon-on-insulator (SOI) MOSFETs. This is mandatory in order to understand the physical mechanisms behind the limitations of the safe operation area (SOA) of SOI power devices. The back-gate electrode of the SOI material will add an additional dimension to the SOA, thereby causing further reliability constraints on the circuit design. For small and negative back-gate bias, the SOA is limited by the ON-state breakdown whereas the OFF-state breakdown sets the limit for positive back-gate bias. For the first time, an analytical model of the breakdown voltage covering the reasonable back-gate voltage range is presented providing a first step toward a closed form circuit simulation of this effect. It is shown that the back-gate potential impacts on the breakdown behavior by modulating the carrier distribution in the drift region, the base transport factor of the parasitic bipolar transistor, and the drift region resistance. Moreover, it is shown that avalanche multiplication is the limiting breakdown mechanism for lateral SOI power devices.Index Terms-Device breakdown, high-voltage, ON-state breakdown, RESURF, silicon-on-insulator (SOI), Smart Power.

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Section: Breakdown Measurementsmentioning

confidence: 95%

Section: Parasitic Bipolar Actionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 98%

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Analysis of the Back-Gate Effect on the on-State Breakdown Voltage of Smartpower SOI Devices

Schwantes¹,

Furthaler²,

Schauwecker³

et al. 2006

IEEE Trans. Device Mater. Relib.

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“…This vertical depletion charge extends the length of the lateral depletion region of the pn-junction consisting of the body and the drift region. This two-dimensional interaction is known as the RESURF effect [6] and improves BVDS [1,2,7]. For large drain voltages, the lateral depletion layer can not extend further towards the drain.…”

Section: Introductionmentioning

confidence: 98%

“…However, the SOI structure introduces an additional electrode, the back gate and with it new physical mechanisms. Recently, the authors have shown that the back gate has a beneficial impact on the drain breakdown voltage BVDS of lateral n-channel DMOS transistors (LDNMOST) and a detrimental effect on the p-channel devices (LDPMOST) [1,2]. Previous works have optimised the LDNMOST only [3,4].…”

Section: Introductionmentioning

confidence: 99%

SOA improvement of P-channel high-voltage SOI devices

Schwantes

Gräf

Dudek

Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005.

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This paper presents a new device structure for smart power SOI technologies. It is shown that the breakdown voltage BVDS and the safe operation area (SOA) of lateral p-channel DMOS transistors can be improved without degrading the on-resistance by locally optimising the gate oxide thickness. New insight into the physical mechanisms taking place in lateral SOI DMOS transistors is presented. For the first time, the impact of the front gate potential on BVDS of p-channel SOI DMOS devices is discussed. The new device structure is benchmarked by its performance and reliability.

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