Analysis of TCP/IP for high performance parallel implementations

Koufopavlou, O.; Tantawy, Ahmed N.; Zitterbart, Martina

doi:10.1109/lcn.1992.228141

Cited by 16 publications

(8 citation statements)

References 4 publications

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“…In the following, we examine possible methods of exploiting parallelism, which could be used in the multiprocessor implementation of the proposed simulator and are usually taken into consideration in parallel designs [22][23][24]. The choice often depends on the structure of the manipulated data, the actions and their properties related to inter-dependencies, or whether they need to be in a specific sequence.…”

Section: Possible Methods For Parallelizationmentioning

confidence: 99%

A batch‐type time‐true ATM‐network simulator—design for parallel processing

Logothetis

Liotopoulos

2002

Int J Communication

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SUMMARYThis paper presents a new type of network simulator for simulating the call-level operations of telecom networks and especially ATM networks. The simulator is a pure time-true type as opposed to a call-by-call type simulator. It is also characterized as a batch-type simulator. The entire simulation duration is divided into short time intervals of equal duration, t: During t; a batch processing of call origination or termination events is executed and the time-points of these events are sorted. The number of sorting executions is drastically reduced compared to a call-by-call simulator, resulting in considerable timesaving. The proposed data structures of the simulator can be implemented by a general-purpose programming language and are well fitted to parallel processing techniques for implementation on parallel computers, for further savings of execution time. We have first implemented the simulator in a sequential computer and then we have applied parallelization techniques to achieve its implementation on a parallel computer. In order to simplify the parallelization procedure, we dissociate the core simulation from the built-in call-level functions (e.g. bandwidth control or dynamic routing) of the network. The key point for a parallel implementation is to organize data by virtual paths (VPs) and distribute them among processors, which all execute the same set of instructions on this data. The performance of the proposed batch-type, time-true, ATM-network simulator is compared with that of a call-by-call simulator to reveal its superiority in terms of sequential execution time (when both simulators run on conventional computers). Finally, a measure of the accuracy of the simulation results is given.

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Section: Possible Methods For Parallelizationmentioning

confidence: 99%

A batch‐type time‐true ATM‐network simulator—design for parallel processing

Logothetis

Liotopoulos

2002

Int J Communication

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“…We use Intel VTune [5] to analyze CPU cycles proportion of the serial reassembly system [6,7]. The results are showed in Table 2.…”

Section: Cpu Cycles Proportion Analysis For Serial Http Packet Reassementioning

confidence: 99%

The optimization of HTTP packets reassembly based on multi-core platform

Yang

Dou

Lei

et al. 2010

2010 2nd IEEE InternationalConference on Network Infrastructure and Digital Content

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HTTP is the most popular application-layer protocol in the Internet. Improving the performance of HTTP packets reassembly is the key point of HTTP traffic analysis. In this paper, we first parallel the traditional serial HTTP packets reassembly system according to the HTTP protocol features. This optimization improves the throughput of packets reassembly system by 45% on the generic multi-core platform. Second, by considering the parallelization extra cost on the multi-core platform, we propose a new method to calculate system speedup based on the Amdahl's law. Furthermore, we make a theoretical analysis to discuss the relationship between system speedup and throughput improvement and then we can estimate the upper bound on throughput improvement.

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“…Earlier work (e.g., [TaKZ94]) has mainly addressed data forwarding and investigated the processing capacity needed for various architectures. [KoTZ94] additionally investigates routing table access and presents an approach based on specialized memory chips, CAMS.…”

Section: Router Architecturementioning

confidence: 99%

“…Since it is less time critical, it is not further investigated within this paper. In [KoTZ94] the routing engine is placed on a centralized processing unit that handles all data related to the control path.…”

Section: Router Architecturementioning

confidence: 99%

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Efficient routing table lookup for IPv6

Zitterbart¹,

Harbaum²,

Meier³

et al.

The Fourth IEEE Workshop on High-Performance Communication Systems

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High performance internetworking units, such as routers and bridges are key building blocks of current and emerging high performance networks. The aggregate data rate flowing through a router can be in the range of gigabits per second. In order to keep up with very high data rates, processing within the internetworking unit needs to be optimized. This paper concentrates on routing table look up. It presents a design for a routing table look up for gigabit routers running the new version of IP, IPv6. The proposed approach, HeaRT, is viewed as the core engine of an IPv6 router.

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Analysis of TCP/IP for high performance parallel implementations

Cited by 16 publications

References 4 publications

A batch‐type time‐true ATM‐network simulator—design for parallel processing

A batch‐type time‐true ATM‐network simulator—design for parallel processing

The optimization of HTTP packets reassembly based on multi-core platform

Efficient routing table lookup for IPv6

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