Analysis of surface potential for dual-material-double-gate MOSFET based on modeling and simulation

Chakrabarti, Himeli; Maity, Reshmi; Maity, N. P.

doi:10.1007/s00542-019-04386-3

Cited by 32 publications

(4 citation statements)

References 23 publications

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“…Transistor count also depends on transistor size. Different high dielectric constant materials are also used for lesser dimension transistor [46][47][48][49][50]. The number of transistor count differs for different adiabatic logic families depending on its schematic structures and energy recovery technique.…”

Section: Resultsmentioning

confidence: 99%

A power efficient fully adiabatic logic circuit design approach: application to inverter and 8421 to excess-3 code converter

Vanlalchaka

Maity

2023

Eng. Res. Express

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Decreasing power consumption is the leading challenge for very-large-scale-integrated (VLSI) designers. This paper introduces an innovative prototype for a power-efficient standard or a fully-adiabatic binary-coded-decimal (BCD) 8421 to Excess-3 (XS-3) code converter. The proposed design is compared with traditional complementary metal oxide semiconductor (CMOS) as well as two popular fully adiabatic logic families: adiabatic dynamic CMOS logic (ADCL) and two phase clocked adiabatic static CMOS logic (2PASCL). This investigation was conducted at frequencies ranging from 100 to 900 MHz. The circuit employs 0.3µm CMOS technology, with channel length and width set at 0.3µm and 0.75µm, respectively. The power savings for the proposed logic at 500 MHz when compared to standard CMOS logic, ADCL, and 2PASCL are 54.54%, 28.57%, and 16.67%, respectively

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Section: Resultsmentioning

confidence: 99%

A power efficient fully adiabatic logic circuit design approach: application to inverter and 8421 to excess-3 code converter

Vanlalchaka

Maity

2023

Eng. Res. Express

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“…With positive trap charges the surface potential curve moves up depicting an increase in the potential and vice-versa can be seen for negative trap charges which are clearly in agreement with. 39 This variation in surface potential is because of trap charges present in the SiO 2 oxide layer. Presence of positive trap charges decreases the energy band gap between n-type (Source/Drain) to ptype (Channel) as shown in Fig.…”

Section: Resultsmentioning

confidence: 99%

Design of Core Gate Silicon Nanotube RADFET with Improved Sensitivity

Chitikina¹,

Mishra²,

Jena³

2022

ECS J. Solid State Sci. Technol.

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The prominent feature of Silicon nanotube metal oxide semiconductor field effect transistor for using radiation-sensitive metal-oxide-silicon field-effect transistor (RADFET) application is its high Ion/Ioff ratio, minimal leakage current and less sensitive to short channel effects. Due to the above features the radiation behaviour of the device is studied to check for the applicability of a RADFET. Here both uniform and non-uniform irradiation characteristics are analysed. The focus of this study is on electrical characteristics and sensitivity, which is measured as variation threshold voltage of radiated and unirradiated device. It was found that on irradiation the surface potential variation is high for 40 nm channel length hence the analysis is conducted for the same. It was proven to be successful, as the device achieves high Ion/Ioff ratio of the order 1013 and a sensitivity of 2.26 mv/Gy. The obtained results are compared with DG RADFET and JL DG RADFET and it shows that Core gate Silicon nanotube RADFET has better electrical characteristics and sensitivity. The simulations are performed in Silvaco 3-D Atlas TCAD simulation software.

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“…Hafnium oxide is employed as a promising gate oxide material because of its excellent interface with Si, high-k value (22), big bandgap (5.6 eV), and conduction band offset (1.4 eV) with regard to Si. Most significantly, a decent electrical interaction with Si makes it a prospective alternative to silicon dioxide [17][18][19][20][21].…”

Section: Structural Dimensions Ie W mentioning

confidence: 99%

Impact of fin width on nano scale tri-gate FinFET including the quantum mechanical effect

et al. 2023

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An inversion charge-based threshold voltage model is proposed for 10 nm channel length Tri-gate (TG) FinFET. The variation threshold voltage has been studied with respect to fin width W f i n for different fin height H f i n and channel length L . The effect of width quantization has been explained with the help of the quantum mechanical effect (QME). A precise comparison of threshold voltage in terms of classical mechanics and quantum mechanics depicts the presence of width quantization in short channel device. The improvement of the short channel effects (SCEs), like subthreshold swing (SS), drain-induced barrier lowering (DIBL) and threshold voltage roll off have been studied. The impact of channel length to fin width ratio on DIBL and S S has been examined. The improvement of the SCEs at the same oxide thickness has been observed for high-k dielectric material. The potential and effect of hafnium oxide (HfO2) have been discussed and validated using technology computer-aided design (TCAD) simulation.

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Analysis of surface potential for dual-material-double-gate MOSFET based on modeling and simulation

Cited by 32 publications

References 23 publications

A power efficient fully adiabatic logic circuit design approach: application to inverter and 8421 to excess-3 code converter

A power efficient fully adiabatic logic circuit design approach: application to inverter and 8421 to excess-3 code converter

Design of Core Gate Silicon Nanotube RADFET with Improved Sensitivity

Impact of fin width on nano scale tri-gate FinFET including the quantum mechanical effect

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