Analysis of SRAM bit failure at high frequency operation

Yoshida, Yoshinori; Funayama, Kota; Nishida, Akio; Sekiguchi, Tomoko; Nakamura, Kiyoji; Tomimatsu, Satoshi; Umemura, K.; Yamanaka, Toshiaki; Komori, Kazuhiro; Mitsui, Yasuhiro; Ikeda, Shuji

doi:10.1109/iedm.1999.824196

Cited by 6 publications

(4 citation statements)

References 4 publications

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“…It was reported that in a failure bit (large V th ) of a MOSFET, a large grain existed in the poly-Si gate. 17) In this MOSFET, T inv was very large owing to LGD. This result indicates that the random size and position of grains in poly-Si cause random V th variation due to random LGD.…”

Section: Lgd Modelmentioning

confidence: 90%

Impact of Oxide Thickness Fluctuation and Local Gate Depletion on Threshold Voltage Variation in Metal–Oxide–Semiconductor Field-Effect Transistors

Putra

Tsunomura

Nishida

et al. 2009

jjap

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We report on the theoretical investigation of how geometrically uniform highly doped silicon nanowires can break up into a series of islands that exhibit Coulomb blockade. By using a newly developed numerical simulation in which random ionized dopants are introduced explicitly and the electron distribution is calculated self-consistently under the Thomas-Fermi approximation, we demonstrate natural formation of electron islands in the nanowires owing to the random dopant potential. We study the quasi-one-dimensional nature of the electron islands formed in the nanowires. The offset charge effects on the current threshold of the nanowire transistors are then investigated by feeding the derived structural parameters such as inter-island capacitance and tunnel resistance into a Monte Carlo single electron transport simulator. We show that the overall threshold voltage distribution can roughly be described as a two-'macro'-island system despite a complex series of multiple electron islands.

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Section: Lgd Modelmentioning

confidence: 90%

Impact of Oxide Thickness Fluctuation and Local Gate Depletion on Threshold Voltage Variation in Metal–Oxide–Semiconductor Field-Effect Transistors

Putra

Tsunomura

Nishida

et al. 2009

jjap

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“…From previous reports, [12][13][14][15][16][17][18][19] it was possible to detect similar abnormal SRAM transistor characteristics by PFA. These characteristics can be detected by the many V th and I ds measurements.…”

Section: Failure Analysis Of Sram With Sg-monos Thermal Budgetmentioning

confidence: 87%

Development of highly reliable static random access memory for 40-nm embedded split gate-MONOS flash memory

Okamoto

Maekawa

Kawashima

et al. 2015

Jpn. J. Appl. Phys.

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High quality static random access memory (SRAM) for 40-nm embedded MONOS flash memory with split gate (SG-MONOS) was developed. Marginal failure, which results in threshold voltage/drain current tailing and outliers of SRAM transistors, occurs when using a conventional SRAM structure. These phenomena can be explained by not only gate depletion but also partial depletion and percolation path formation in the MOS channel. A stacked poly-Si gate structure can suppress these phenomena and achieve high quality SRAM without any defects in the 6σ level and with high affinity to the 40-nm SG-MONOS process was developed.

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“…Snyder et al 6 analyzed reasons for failure of chips working at very high frequency. Ikeda et al 7 and Yoshida et al 8 used techniques such as nanoprobes, selective etching and TEM observations to analyze bit failures at low voltage and high operating speed.…”

Section: Introductionmentioning

confidence: 99%

On-board SRAM signal density stress prediction

Hsieh

Sharma

2006

SPIE Proceedings

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Static Random Access Memory (SRAM) chips undergo several types of stress in the field. Existing work has concentrated primarily on humidity and thermal stress; there has been relatively little emphasis on signal density stress prediction. Objectives of this study were to (1) explore the impact of signal density stress on SRAM functionality, (2) observe thermal profile differences under signal density stress over time, (3) predict stress levels using artificial neural network models, and (4) develop a generic methodology for signal density stress prediction. An 8051 programming board containing an SRAM chip was used. Two kinds of signal density stress were investigated-varying the content written to memory, and varying signal frequency in accessing SRAM through flash memory. Preliminary experiments suggest that both types of stress impact the SRAM thermal profile. Thermal profile data were used to build back propagation neural network models; 70% of the data was used to build the models and 30% was used for testing. Various neural network training functions and topologies were used to predict chip stress level given thermal profile data. Data from both the die area and the entire chip were used. For both types of stress, using data from the die area in a network with a 3-3-1 topology yielded the lowest average error rate-1.3% for data content stress level prediction and 7.6 % for signal frequency stress level prediction. The trainRP function resulted in a lower error rate than other training functions that were evaluated.

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Analysis of SRAM bit failure at high frequency operation

Cited by 6 publications

References 4 publications

Impact of Oxide Thickness Fluctuation and Local Gate Depletion on Threshold Voltage Variation in Metal–Oxide–Semiconductor Field-Effect Transistors

Impact of Oxide Thickness Fluctuation and Local Gate Depletion on Threshold Voltage Variation in Metal–Oxide–Semiconductor Field-Effect Transistors

Development of highly reliable static random access memory for 40-nm embedded split gate-MONOS flash memory

On-board SRAM signal density stress prediction

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