Analysis of Single-Event Upsets and Transients in 22 nm Fully Depleted Silicon-On-Insulator Logic

D'Amico, Joseph V.; Vibbert, S. T.; Watkins, A. C.; Fahrenkrug, Benjamin C.; Haeffner, T. D.; Ball, D. R.; Sternberg, Andrew L.; Alles, Michael L.; Kauppila, J. S.; Massengill, L.W.

doi:10.1109/tns.2023.3237178

Cited by 2 publications

(1 citation statement)

References 27 publications

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“…It has been proven that the soft error rate (SER) with a 28 nm Ultra-Thin Body and BOX (UTBB) is almost two orders of magnitude lower than with similar 28 nm bulk technology [8][9][10][11][12][13][14]. Previous studies have focused on the Single-Event Upset (SEU) characteristics, total-dose ionizing responses, and simulations of FDSOI technology [15][16][17][18][19]. However, it was found that soft errors resulting from SETs in combinational logic circuits surpassed those resulting from SEUs in storage circuits, such as flip-flops and SRAM, when the combinational logic circuit operates at a high frequency [6,[20][21][22][23].…”

Section: Introductionmentioning

confidence: 99%

Single-Event Transient Study of 28 nm UTBB-FDSOI Technology Using Pulsed Laser Mapping

Rui

Chen

et al. 2023

Electronics

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Single-event transient (SET)-induced soft errors are becoming a more significant threat to the reliability of electronic systems in space, especially for advanced technologies. The SET pulse width, which is vulnerable to SET propagation, is a critical parameter for developing SET mitigation techniques. This paper investigates the pulse-broadening effect in the process of SET propagation in logic circuits and the SET-sensitive region distribution in the layout using the pulsed-laser mapping technique in logic circuits implemented with 28 nm Ultra-Thin Body and BOX (UTBB) FDSOI technology. The experiments were carried out at the Naval Research Laboratory (NRL) to measure the SET-induced errors and map the SET-sensitive region distribution at various clock frequencies and laser energy levels. The results illustrate that the number of errors increases with the clock frequency and energy for combinational logic circuits and that the flip-flop SEU rate is less sensitive to clock frequency. The SET pulse-broadening effect was also observed using SET mapping for an OR gate chain at different laser energy levels. In addition, the simulation results revealed the mechanism of the SET pulse-broadening effect in an OR gate chain.

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