Analysis of short channel characteristics in graded channel dual-material elliptical gate-all-around (GC DM EGAA) MOSFET

Abstract

A comprehensive investigation of the subthreshold behavior of a graded channel dual-material elliptical gate-all-around MOSFET has been presented in this research. Detailed analysis of the device's immunity over the various short channel effects like threshold voltage roll-off, draininduced barrier lowering, subthreshold swing and hot carrier effect have been conducted using the central potential where the latter has been derived using the quasi-3-D scaling length concept. The analytical results have been verified using ATLAS simulation data.

A 2-D compact DC model for engineered nanowire JAM-MOSFETs valid for all operating regimes

“…Figure 2(a) shows the calibration of the simulation setup with the experimental results of [31] at V GS = 1 and 0.1 V, in both linear and logarithmic scale. Figure 2(b) demonstrates validation of our proposed model with that of the device model proposed for JLAMSG MOSFET in [4], JLDMCSG MOSFET in [6] and Circular GCDMG MOS-FET in [9]. Therefore our numerical simulations match well with experimental results and our proposed analytical model matches well with other reported analytical models.…”

“…For figure 3(b) it could be observed that the electric field at drain end increases with L 1 : L 2 , (increase in HCEs). Therefore, SCEs decreases and HCEs increase with L 1 :L 2 [9]. Thus for further comparisons, we have optimized L 1 :L 2 to 1:1.…”

“…Device engineering [4] No Yes No [6][7][8][9] No Yes Yes [14,15] Yes No No Our Model Yes Yes Yes to yield higher drive current due to reduced source-drain resistance and higher channel mobility. The device also has reduced RDF effects due to reduced channel doping.…”

“…Device engineering techniques such as gate-electrode material engineering (e.g. using a dual-material (DM) gateelectrode) [6][7][8], graded channel GC) engineering [8,9], and gate oxide engineering (e.g. using a lateral/vertical stacked hetero-dielectric (SHD) to form the resultant gate oxide) [7] have been explored independently or in a combination of more than one technique for reducing SCEs, DIBLs, and leakage currents.…”

“…Although some 2-D continuous potential based models are reported for the MOS devices, but they are valid either for only depletion regime (i.e. by considering only depletion charges) [4,[6][7][8][9] or only for accumulation/inversion regime (i.e. by considering only free mobile charges) [14,15] of operation as summarized in table 1.…”