“…Device engineering techniques such as gate-electrode material engineering (e.g. using a dual-material (DM) gateelectrode) [6][7][8], graded channel GC) engineering [8,9], and gate oxide engineering (e.g. using a lateral/vertical stacked hetero-dielectric (SHD) to form the resultant gate oxide) [7] have been explored independently or in a combination of more than one technique for reducing SCEs, DIBLs, and leakage currents.…”