Analysis of SEU Propagation in Combinational Circuits at RTL Based on Satisfiability Modulo Theories

Accelerating stochastic‐based reliability estimation for combinational circuits at RTL using GPU parallel computing

“…Shazli and Tahoori 27 transformed the reliability problem into an equivalent Boolean satisfiability (SAT) problem and used SAT‐solvers to obtain the soft error rate of the given circuits. However, the model has high complexity when dealing with basic RTL arithmetic operations 22 . By Kazma et al, 22 an approach was proposed to model the propagation of the faults as an SAT problem using satisfiability modulo theories to estimate the vulnerability of combinational circuits to soft errors, in which the data‐type reduction technique presented by Chen et al 26 was applied to reduce the difficulty of the problem being analyzed.…”

“…10,[19][20][21] They are often used to quickly and efficiently calculate the reliability of combinational circuits and identify the reliability-critical gates. 15,21 However, they are not conducive to measuring the reliability of the functional blocks that make up the circuits, 22,23 which makes them unfavorable for the implementation of selective hardening operations based on functional blocks. Therefore, the propagation of soft errors in logic circuits was analyzed at register transfer level (RTL) by various researchers using fault simulation 24,25 and formal verification methods.…”