Analysis of quasi-static scheduling techniques in a virtualized reconfigurable machine

Markovskiy, Yury; Caspi, Eylon; Huang, Randy; Yeh, Joseph; Chu, Michael; Wawrzynek, John; DeHon, André

doi:10.1145/503074.503077

Cited by 3 publications

(5 citation statements)

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“…Another use case is the guidance of backends. For coarse-grained rFPGAs, the results can guide the partitioning of applications into synthesizable configurations or direct quasi-static scheduling to reduce runtime overhead [14].…”

Section: Discussionmentioning

confidence: 99%

Static run-time mode extraction by state partitioning in synchronous process networks

Beyer

Glesner

2011

Proceedings of the 14th International Workshop on Software and Compilers for Embedded Systems

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Process Networks (PNs) are used for modeling streamingoriented applications with changing behavior, which must be mapped on a concurrent architecture to meet the performance and energy constraints of embedded devices. Finding an optimal mapping of Process Networks to the constrained architecture presumes that the behavior of the PN is statically known. In this paper we present a static analysis for synchronous PNs that partitions the state space according to extract run-time modes based on a Data Augmented Control Flow Automaton (DACFA). The result is a mode automaton whose nodes describe identified program modes and whose edges represent transitions among them. Optimizing backends mapping from PNs to concurrent architectures can be guided by these analysis results.

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Section: Discussionmentioning

confidence: 99%

Static run-time mode extraction by state partitioning in synchronous process networks

Beyer

Glesner

2011

Proceedings of the 14th International Workshop on Software and Compilers for Embedded Systems

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“…We have developed a series of schedulers to address these issues, as previously reported [19,53,52]. In this section, we highlight the lessons from those exercises.…”

Section: Schedulingmentioning

confidence: 99%

“…It yields makespans that are within 17% of the optimal single-appearance schedule [53], yet it consumes only 300-700 thousand processor cycles (measured on a Pentium III using on-chip time-stamp counter; see Table 3). Even on a 100 MHz processor, this means schedule generation time would be only 3-7 ms.…”

Section: Partitioning and Schedulingmentioning

confidence: 99%

Stream Computations Organized for Reconfigurable Execution

DeHon¹,

Markovskiy²,

Caspi³

et al. 2008

Reconfigurable Computing

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Reconfigurable systems can offer the high spatial parallelism and fine-grained, bit-level resource control traditionally associated with hardware implementations, along with the flexibility and adaptability characteristic of software. While reconfigurable systems create new opportunities for engineering and delivering high-performance programmable systems, the traditional approaches to programming and managing computations used for hardware systems (e.g., Verilog, VHDL) and software systems (e.g., C, Fortran, Java) are inappropriate and inadequate for exploiting reconfigurable platforms. To address this need, we develop a stream-oriented compute model, system architecture, and execution patterns which can capture and exploit the parallelism of spatial computations while simultaneously abstracting software applications from hardware details (e.g., timing, device capacity, and microarchitectural implementation details) and consequently allowing applications to scale to exploit newer, larger, and faster hardware platforms. Further, we describe hardware and software techniques that make this late-bound platform mapping viable and efficient.

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“…Here, we focus entirely on routing and leave partitioning and placement as separate issues. Fast software partitioning is treated in part in our recent paper on quasistatic scheduling [1]. Callahan demonstrates one approach to fast, 1-D, datapath placement [2].…”

Section: Motivationmentioning

confidence: 99%

“…Design information is summarized in Table 1. Placement is performed by the SCORE scheduler [1], and the same placement is used for all routing experiments. Synthetic Benchmark Although it is important to have netlists from real applications, the SCORE netlists are moderately small and are likely to be moderately easy to route.…”

Section: Benchmarksmentioning

confidence: 99%