Analysis of Noise in Current Mirror Circuits Based on CNTFET and MOSFET

Self Cite

In this paper initially we present two CNTFET models: the first, already proposed by us and the second the Stanford model, recalling our method to match the output characteristics and transconductance characteristics between these two models. Then we briefly recall a compact noise model, proposed by us, used to simulate the performance of some digital CNTFET circuits, for which we present the DC, transient and noise analysis. In particular we examine a inverter gate and the proposed analysis allows to determine the optimal value of input voltage which makes the noise effects negligible.

Section: A Brief Review Of Methods To Match the Examined Modelsmentioning

confidence: 99%

Noise Effects in the Design of Digital Circuits Based on CNTFET

Marani¹,

Perri²

2022

Self Cite

“…Considering the noise margin for high logic level (NM H ) and the noise margin for low level (NM L ), the voltage levels must be determined by the VTC points where the absolute value of differential gain is equal or greater than 1, as we have explained in Ref. 23.…”

Section: Cntfet Not Gatementioning

confidence: 99%

Review—Design and Characterization of Digital Gates based on CNTFET and CMOS Technology

Marani¹,

Perri²

2022

Self Cite

In this paper we review a procedure to design and characterize logic gates based on CNTFET and CMOS technology. For the first technology we use a CNTFET model, already proposed by us, while for the second one we use the BSIM4 model of the Advanced Design System (ADS) library. In particular we consider NAND and NOT gates at different supply voltages and frequencies, for both technologies. The optimal results, obtained using the simulator ADS, are at 0.5 V and 50 GHz for CNTFET, while for CMOS technology at 3 V and 200 MHz. Moreover we quantitatively show the comparison between the two considered technologies in term of delay and power delay product (PDP).

“…In particular we have studied extensively MOSFET-like CNTFET for high-performance and low-power memory designs. [12][13][14][15][16][17][18][19][20][21][22] In this review we present many design of CNTFET-based circuits, already proposed by us and here critically examined.…”

mentioning

confidence: 99%

Review—Critical Analysis of CNTFET-Based Electronic Circuits Design

Marani¹,

Perri²

2023

Self Cite

In this review we present many designs for carbon nanotube field effect transistor (CNTFET)-based circuits, already proposed by us and here critically examined. For some of these, we compare the performance of proposed circuits both in CNTFET and complementary metal oxide semiconductor technology. For the CNTFET model, we use a compact, semi-empirical model, while, for the metal oxide semiconductor field effect transistor model, we use the BSIM4 one of ADS library. Moreover in some design examples we compare our results with those obtained using the Stanford model. All simulations are carried out using the software advanced design system, which is compatible with the Verilog-A programming language.