Analysis of Negative Differential Resistance and RF/Analog Performance on Drain Engineered Negative Capacitance Dual Stacked-Source Tunnel FET

Vanlalawmpuia, K.; Medury, Aditya

doi:10.1109/ted.2023.3237507

Cited by 5 publications

(4 citation statements)

References 35 publications

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“…The proposed NC Ge-vTFET has been benchmarked with other existing negative capacitance FETs as tabulated in table 3. The channel length of the Germanium source NC-TFET [49] is 30 nm, while L G of the Gate-Normal NCTFET [30], NCDSS-TFET [39] and NC-Ge-vTFET (this work) are 50 nm, 40 nm, and 45 nm, respectively. It is evident that the optimized NC Ge-vTFET device with mitigated NDR effect possesses superior electrical performance.…”

Section: Benchmarkingmentioning

confidence: 95%

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Investigation of negative differential resistance on negative capacitance Germanium source vertical TFET

Vanlalawmpuia

2024

Phys. Scr.

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In this article, a systematic investigation of negative differential resistance (NDR) on a negative capacitance Germanium source vertical TFET (NC-Ge-vTFET) is presented. The implementation and increased ferroelectric (FE) film thickness (tFE) offers a significantly high current ratio, improved subthreshold slope, high transconductance with a very low hysteresis voltage. However, NDR is exhibited and is increasingly prominent at lower gate voltage and higher tFE due to the coupling of the internal gate and drain voltages. NDR is an undesired effect in analog circuits that has to be mitigated. To suppress the impacts of NDR on the device, different approaches are carried out: varying the overlap channel thickness, gate length, drain doping and gate-drain underlap. Circuit analysis is carried out with the implementation of NC-Ge-vTFET as digital inverter. When the gate-drain underlap length is increased from 0 nm to 15 nm, the propagation delay is significantly reduced by 30.98%. Benchmarking of the proposed device has also been carried out. This renders the gate-drain underlapped NC-Ge-vTFET to be a viable candidate for high performance, nanoscale, low power digital applications.

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Section: Benchmarkingmentioning

confidence: 95%

“…Furthermore, using a drain-side Paraelectric (PE) spacer, in addition to reduced drain doping, the NDR impact can also be lowered [38]. Recently, the NDR effects on tunnel FET have been investigated [39], however, the analysis is carried out only for lateral or point band-to-band tunneling TFET.…”

Section: Introductionmentioning

confidence: 99%

Investigation of negative differential resistance on negative capacitance Germanium source vertical TFET

Vanlalawmpuia

2024

Phys. Scr.

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“…In this work, we have adopted an approximation method 5 from [51] for approximate SRAM CiM full adder. If A, B, and C in are the inputs to the NCFET based SRAM CiM full adder (FA), then the outputs Sum and C out can be approximated by the equations ( 5) and ( 6) [46] as…”

Section: Reconfigurable (Accurtae and Approximate) Ncfet Based 6t-sra...mentioning

confidence: 99%

“…The MIT model has captured various distinctive characteristics of NCFETs. The NCFET device model parameters are presented in table 1 [46,47].…”

Section: Overview Of Ncfet Device Structure Ncfet Based 6t Sram Cell ...mentioning

confidence: 99%

Computing in-memory reconfigurable (accurate/approximate) adder design with negative capacitance FET 6T-SRAM for energy efficient AI edge devices

Venu,

Kadiyam,

Penumalli

et al. 2024

Semicond. Sci. Technol.

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Computing in-memory (CiM) is an alternative to von-Neumann architectures for energy efficient AI edge computing architectures with CMOS scaling. Approximate computing in-memory (ACiM) techniques have also been recently proposed to further increase the energy efficiency of such architectures. In the first part of the work, a Negative Capacitance FET (NCFET) based 6T-SRAM CiM accurate full adder has been proposed, designed and performance benchmarked with equivalent baseline 40nm CMOS design. Due to the steep slope characteristics of NCFET, at an increased ferroelectric layer thickness, Tfe of 3nm, the energy consumption of the proposed accurate NCFET based CiM design is ~82.48% lower in comparison to the conventional/Non CiM full adder design and ~ 85.27% lower energy consumption in comparison to the equivalent baseline CMOS CiM accurate full adder design at VDD = 0.5V. This work further proposes a reconfigurable computing in-memory NCFET 6T-SRAM full adder design (the design which can operate both in accurate and approximate modes of operation). NCFET 6T-SRAM reconfigurable full adder design in accurate mode has ~4.19x lower energy consumption and ~4.47x lower energy consumption in approximation mode when compared to the baseline 40nm CMOS design at VDD=0.5V, making NCFET based approximate CiM adder designs preferable for energy efficient AI edge CiM based computing architectures for DNN processing.

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Performance investigation of ferroelectric L-shaped tunnel FET with suppressed corner tunneling for low power applications

Pathakamuri,

Pandey

2024

AEU - International Journal of Electronics and Communications

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Analysis of Negative Differential Resistance and RF/Analog Performance on Drain Engineered Negative Capacitance Dual Stacked-Source Tunnel FET

Cited by 5 publications

References 35 publications

Investigation of negative differential resistance on negative capacitance Germanium source vertical TFET

Investigation of negative differential resistance on negative capacitance Germanium source vertical TFET

Computing in-memory reconfigurable (accurate/approximate) adder design with negative capacitance FET 6T-SRAM for energy efficient AI edge devices

Performance investigation of ferroelectric L-shaped tunnel FET with suppressed corner tunneling for low power applications

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