Analysis of multiple cell upset sensitivity in bulk CMOS SRAM after neutron irradiation

Pan, Xiaoyu; Guo, Hao; Luo, Yan-An; Zhang, Fengqi; Ding, Lili

doi:10.1088/1674-1056/27/3/038501

Cited by 3 publications

(1 citation statement)

References 11 publications

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“…Hence, it is extremely necessary to take SEE into account and evaluate this risk comprehensively. [9][10][11][12] SoC integrates multiple high-performance processing units in one single chip. The advantages of weight, performance, and power consumption assist it to be listed in the space application candidates.…”

Section: Introductionmentioning

confidence: 99%

Investigation of single event effect in 28-nm system-on-chip with multi patterns*

Wu¹,

Li²,

Guo³

et al. 2020

Chinese Phys. B

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Single event effects (SEEs) in a 28-nm system-on-chip (SoC) were assessed using heavy ion irradiations, and susceptibilities in different processor configurations with data accessing patterns were investigated. The patterns included the sole processor (SP) and asymmetric multiprocessing (AMP) patterns with static and dynamic data accessing. Single event upset (SEU) cross sections in static accessing can be more than twice as high as those of the dynamic accessing, and processor configuration pattern is not a critical factor for the SEU cross sections. Cross section interval of upset events was evaluated and the soft error rates in aerospace environment were predicted for the SoC. The tests also indicated that ultra-high linear energy transfer (LET) particle can cause exception currents in the 28-nm SoC, and some even are lower than the normal case.

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Section: Introductionmentioning

confidence: 99%

Investigation of single event effect in 28-nm system-on-chip with multi patterns*

Wu¹,

Li²,

Guo³

et al. 2020

Chinese Phys. B

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Analysis of multiple cell upset characteristics for logical circuits in radiation environment

Ding

Wang

Zhang

et al. 2020

Nuclear Instruments and Methods in Physics Research Section A:

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Mutual interference induced by single event effects in CMOS circuits

et al. 2020

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Single event effect (SEE) induced mutual interference in CMOS circuits, including single event (SE) induced coupling effects (crosstalk) and modulation in local supply voltage on power-supply rails, was studied based on the increase in metal interconnect density. The dependence of SE vulnerability on metal interconnects was experimentally investigated using heavy ions and pulsed laser. Numerical simulation was performed to evaluate the modulation in local supply voltage induced by SEEs. Two groups of test structures with various metal interconnects between well contacts and the first metal layer were designed and fabricated. All other parts, including well contacts in the active regions, are of the same structures. Experimental results show that the upset cross section decreases with an increase in metal interconnect contact (CT) density between the active region and the first metal layer, suggesting a dominant contribution of rail voltage drop induced by charge sharing rather than SE-induced crosstalk. The differences in upset cross sections with cells of different CT hole densities appear the most evident ones under low frequency and high linear energy transfer value conditions. When transient-induced upsets play a more important role, the differences get weakened due to masking effects.

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Analysis of multiple cell upset sensitivity in bulk CMOS SRAM after neutron irradiation

Cited by 3 publications

References 11 publications

Investigation of single event effect in 28-nm system-on-chip with multi patterns*

Investigation of single event effect in 28-nm system-on-chip with multi patterns*

Analysis of multiple cell upset characteristics for logical circuits in radiation environment

Mutual interference induced by single event effects in CMOS circuits

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