As a complement to testing procedures, verification techniques as e.g. model checking have been proposed to analyze logic controllers specified as Sequential Function Charts (SFC). For the success of these techniques suitable execution models of the SFC and of the programmable logic controllers (PLC) on which the SFC are implemented and operated in practice are crucial. This paper investigates and compares two different recently suggested transformation schemes for mapping SFC into timed automata (TA): an event-triggered and a cycle driven scheme. For the example of a laboratory experiment, the paper shows how the schemes lead to TA models of the controller which can, when complemented with appropriate plant models, be used for verifying properties as e.g. safety by employing the software tool UPPAAL. The event-triggered transformation scheme is found to lead to considerably smaller TA models and hence to be more suitable for verification purposes.
I. INTRODUCTIONLogic controllers specified as Sequential Function Charts (SFC) have become increasingly popular in the process and manufacturing industry. SFC are defined in the standard IEC 61131-3 [7] as one of five programming languages for programmable logic controllers (PLC). These are standard devices for sequential control due to their robustness and reliability, and are often embedded into hierarchical automation architectures for larger plants.The correctness of SFC programs implemented on PLC is obviously crucial for the overall success and the safety of plant operation. While the design of the control programs becomes increasingly more complex due to a larger number of functions included, competitive markets require shorter development and start-up times. In order to reduce the time needed to check the correctness of the PLC programs, verification can be a valuable substitute of testing, as it replaces the tedious (manual) choice of scenarios to be investigated by an algorithmic search over all possible cases and executions. If appropriate plant models are available, algorithmic verification by model checking [4] can prove that the logic controller controls the plant such that requirements as e.g. safety, goalattainment, or deadlock-avoidance are achieved.In order to apply model checking to the control program, the SFC (which is a partly graphical repre-