Abstract:Modern semiconductor industry has a major focus on die size reduction and favours the usage of multiple metal layers to increase gross margins. High congestion and voltage or IR drop challenges result from designs with higher and lower core utilisations. Owing to this issue, one of the major difficulties in large silicon-on-chip (SoC) design is the implementation of a power grid design. It’s essential to correctly analyze IR drops to guarantee the reliability of the power grid. This paper presents a comprehens… Show more
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