We observe many CMOS circuits that consume very high power in recent times. In addition to that of the CMOS family, many logic styles were improved to increase the performance of full adder circuit. Designing existing full adder logic styles in both 90nm and 130nm and compared with proposed logic style. To through the power item, introducing energy efficient full adder with 10 transistors in both 90nm and 130nm technology. All the full adders are planned to investigate in terms of power. The results show that all the models proposed are energy efficient. Finally, power consumed by the full adder cell in comparison with the old designs has been achieved. For meeting the demands of fast progressive era of electronics most efficient full adder structure is developed.